Avoiding unknown states when scanning mutually exclusive latches

Many modern circuits contain logic which must be controlled with mutually exclusive (one-out-of-n) control signals. Common examples include controls to 3-state buses and pass-gate multiplexers. If these control signals are allowed to attain any value combination other than one-out-of-n, the controlled logic may produce an unknown (X) state. In a scan based design, these mutually exclusive signals become problematic if they must be stored in latches. Mutually exclusive values will typically not be maintained on the outputs of these latches during scanning, nor as final values if random test patterns are scanned in. This paper describes a hardware technique that places logic in the scan path to ensure that a given set of latches always maintains mutually exclusive values during scanning.

[1]  Thomas W. Williams,et al.  Design for Testability - A Survey , 1982, IEEE Trans. Computers.

[2]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[3]  L. Y. Ungar.  Built-in test IC provides automatic test equipment capabilities , 1991, Conference Record AUTOTESTCON '91 IEEE Systems Readiness Technology Conference Improving Systems Effectiveness in the Changing Environment of the '90s.

[4]  S.M. Reddy,et al.  On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Parker,et al.  Design for Testability—A Survey , 1982, IEEE Transactions on Computers.

[6]  M. M. Pradhan,et al.  Circular BIST with partial scan , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[7]  S. Pateras,et al.  Cost trade-offs of various design for test techniques , 1994, Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing.

[8]  Andrzej Krasniewski,et al.  Circular self-test path: a low-cost BIST technique for VLSI circuits , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Srinivas Patil,et al.  Scan-based transition test , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[11]  Rabindra K. Roy,et al.  The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.

[12]  B. Koenemann,et al.  Built-in logic block observation techniques , 1979 .