A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs

The authors present a statistics-based blind calibration technique for nonlinear memory errors in amplifier-sharing pipelined ADCs. The proposed method is fully digital and simple to implement. It detects memory errors in normal operation without system suspension for calibration. No special calibration signal or analog circuitry is necessary. Algorithm description and simulation results are presented. The proposed technique improves the power efficiency of pipelined ADCs by enabling sharing of low-gain operational amplifiers.

[1]  Byung-Moo Min,et al.  A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC , 2003, IEEE J. Solid State Circuits.

[2]  Hae-Seung Lee,et al.  A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[3]  T. Yamaji,et al.  55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[4]  Stephen H. Lewis,et al.  Digital background calibration for memory effects in pipelined analog-to-digital converters , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  A. Karanicolas,et al.  A 15 b 1 Ms/s digitally self-calibrated pipeline ADC , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[6]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[7]  P.R. Gray,et al.  A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR , 2004, IEEE Journal of Solid-State Circuits.

[8]  Stephen H. Lewis,et al.  A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers , 1997, IEEE J. Solid State Circuits.