A novel combinational testability analysis by considering signal correlation

To predict the difficulty of testing a wire stuck-at fault, testability analysis algorithms provide an estimated testability value by computing controllability and observability. In all previous work, signal correlation between controllability and observability is generally ignored. As a result, the estimated value can be inaccurate. This paper discusses an efficient method to take into account signal correlation for testability analysis. Our experimental results have shown that, with little run time overhead, significant improvement of testability analysis can be achieved.

[1]  Dhiraj K. Pradhan,et al.  Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci , 1992, Proceedings International Test Conference 1992.

[2]  Franc Brglez,et al.  Testability-Driven Random Test-Pattern Generation , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[4]  F. Brglez,et al.  On testability of combinational networks , 1984 .

[5]  Nur A. Touba,et al.  Test point insertion based on path tracing , 1996, Proceedings of 14th VLSI Test Symposium.

[6]  Kwang-Ting Cheng,et al.  Timing-driven test point insertion for full-scan and partial-scan BIST , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[7]  Sunil Jain,et al.  Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.

[8]  Vishwani D. Agrawal,et al.  AN EXACT ANALYSIS FOR EFFICIENT COMPUTATION OF RANDOM-PATTERN TESTABILITY IN COMBINATIONAL CIRCUITS , 1986 .

[9]  Rhonda Kay Gaede,et al.  Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm , 1986, ITC.

[10]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[11]  Harry B. Hunt,et al.  On Computing Signal Probability and Detection Probability of Stuck-at Faults , 1990, IEEE Trans. Computers.

[12]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[13]  Jacob Savir,et al.  On Random Pattern Test Length , 1984, IEEE Transactions on Computers.

[14]  Janusz Rajski,et al.  Constructive multi-phase test point insertion for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[15]  M. Koudil,et al.  Automatic test point insertion for pseudo-random testing , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[16]  P. R. Schneider,et al.  On the necessity to examine D-chains in diagnostic test generation-an example , 1967 .

[17]  Jacob Savir,et al.  Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.

[18]  L. H. Goldstein,et al.  Controllability/observability analysis of digital circuits , 1978 .

[19]  Kwang-Ting Cheng,et al.  A hybrid algorithm for test point selection for scan-based BIST , 1997, DAC.