Optimum Reduction of Programmable Logic Array

We consider the optimum PLA column folding problem where vertices in the column intersection graph are first partitioned into two parts. Both upper and lower bounds on the size of the folding are given in terms of the number of edges and vertices in the bipartite graph G. Efficient polynomial optimum algorithms are given for the case that G is a tree and other cases. A heuristic algorithm with error bound is given for a general bipartite graph. A new graph model is introduced. We also study one-cut bipartite folding, AND-OR-AND row folding, and the general partitioning problem.

[1]  Werner Grass A Depth-First Branch-and-Bound Algorithm for Optimal PLA Folding , 1982, 19th Design Automation Conference.

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  Techniques for Programmable Logic Array Folding , 1982, 19th Design Automation Conference.

[3]  Roy A. Wood A High Density Programmable Logic Array Chip , 1979, IEEE Transactions on Computers.

[4]  T. C. Hu,et al.  Multi-Terminal Network Flows , 1961 .

[5]  Alberto L. Sangiovanni-Vincentelli,et al.  An Algorithm for Optimal PLA Folding , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  J. R. Egan,et al.  Optimal Bipartite Folding of PLA , 1982, DAC 1982.

[7]  S. Vajda,et al.  Integer Programming and Network Flows , 1970 .