A WSI macrocell fault circumvention strategy

The use of a design paradigm that consists of a hierarchy of structures from cells to macrocells to functional elements to wafers greatly simplifies the design and development of wafer scale integration (WSI) systems. The authors examine the use of pooled spares, for fault circumvention at the macrocell level of the hierarchy. A method is provided that maximizes the yield of the pools of macrocells as a function of the yield of individual macrocells and the yield of the interconnection network. An example shows the application of this theory to a floating-point complex butterfly for signal processing applications.<<ETX>>