Compact models and computation of crosstalk for sub-threshold interconnect circuits

In this paper, an analytical framework to model crosstalk in sub-threshold regime of buffer driven coupled interconnects has been presented. Sub-threshold current model is used to represent the transistor. Propagation delay and timing are determined for the conditions when inputs to the coupled interconnect are switching in-phase and out-of-phase. Analytical expressions governing peak noise have also been presented. A comparative analysis of the analytical results with SPICE simulations shows that the proposed models capture waveform shape, propagation delay, timing and noise peaks with good accuracy. It is also analyzed that crosstalk is influenced by variation in the interconnect parameters namely length, width, adjacent spacing and buffer size.

[1]  Massimo Alioto,et al.  Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Jason Helge Anderson,et al.  Low-Power Programmable FPGA Routing Circuitry , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Q.H. Liu,et al.  Crosstalk Prediction of Single- and Double-Walled Carbon-Nanotube (SWCNT/DWCNT) Bundle Interconnects , 2009, IEEE Transactions on Electron Devices.

[4]  David Blaauw,et al.  Modeling and analysis of crosstalk noise in coupled RLC interconnects , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Benton H. Calhoun,et al.  Device sizing for minimum energy operation in subthreshold circuits , 2004 .

[6]  S. Subash,et al.  A New Spatially Rearranged Bundle of Mixed Carbon Nanotubes as VLSI Interconnection , 2013, IEEE Transactions on Nanotechnology.

[7]  S. D. Pable,et al.  High speed interconnect through device optimization for subthreshold FPGA , 2011, Microelectron. J..

[8]  Selahattin Sayil,et al.  Single Event crosstalk shielding for CMOS logic , 2009, Microelectron. J..

[9]  Hassan Fathabadi.  Ultra Low Power Improved Differential Amplifier , 2013, Circuits Syst. Signal Process..

[10]  Anantha Chandrakasan,et al.  Sub-threshold Design for Ultra Low-Power Systems , 2006, Series on Integrated Circuits and Systems.

[11]  Yingchieh Ho,et al.  Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[12]  A. Wang,et al.  Modeling and sizing for minimum energy operation in subthreshold circuits , 2005, IEEE Journal of Solid-State Circuits.

[13]  James D. Meindl,et al.  Compact distributed RLC interconnect models - part III: transients in single and coupled lines with capacitive load termination , 2003 .

[14]  Eby G. Friedman,et al.  Data bus swizzling in TSV-based three-dimensional integrated circuits , 2013, Microelectron. J..

[15]  Rajeevan Chandel,et al.  An analysis of interconnect delay minimization by low-voltage repeater insertion , 2007, Microelectron. J..

[16]  Eby G. Friedman,et al.  The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections , 2002 .