Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

For the first time, we report a short channel high performance, gate-all-around strained Si<inf>0.4</inf>Ge<inf>0.6</inf> nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si<inf>0.4</inf>Ge<inf>0.6</inf> nanosheet with 5nm thickness and device with L<inf>G</inf>=25nm featuring record high I<inf>ON</inf>=508 µA/µm at I<inf>OFF</inf>=100nA/µm and V<inf>DS</inf>= -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D<inf>IT</inf> and N<inf>IT</inf> for s-Si<inf>0.4</inf>Ge<inf>0.6</inf> channel, (b) record high hole mobility= 450 cm²/Vs owing to compressive strain imparted by Si<inf>0.7</inf>Ge<inf>0.3</inf> strain relaxed buffer (SRB), (c) low R<inf>EXT</inf>=150 Ω-µm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I<inf>OFF</inf>. Additionally, the impact of operating temperature on GIDL and I<inf>OFF</inf> is comprehensively studied to prescribe optimal V<inf>CC</inf> range of operation for this technology.