Digital Design Using VHDL: A Systems Approach

This introductory textbook provides students with a system-level perspective and the tools they need to understand, analyze and design digital systems. Going beyond the design of simple combinational and sequential modules, it shows how such modules are used to build complete systems, reflecting real-world digital design. All the essential topics are covered, including design and analysis of combinational and sequential modules, as well as system timing and synchronization. It also teaches how to write VHDL-2008 HDL in a productive and maintainable style that enables CAD tools to do much of the tedious work. A complete introduction to digital design is given through clear explanations, extensive examples and online VHDL files. The teaching package is completed with lecture slides, labs and a solutions manual for instructors. Assuming no previous digital knowledge, this textbook is ideal for undergraduate digital design courses that will prepare students for modern digital practice.

[1]  Ivan E. Sutherland,et al.  Logical effort: designing for speed on the back of an envelope , 1991 .

[2]  Nick Tredennick Microprocessor logic design: The flowchart method , 1987 .

[3]  R. E. Meagher,et al.  The ORDVAC , 1951, AIEE-IRE '51.

[4]  George Boole,et al.  The mathematical analysis of logic , 1948 .

[5]  Edward F. Moore,et al.  Gedanken-Experiments on Sequential Machines , 1956 .

[6]  William J. Dally,et al.  Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[7]  Keith Baker,et al.  Shmoo Plotting: The Black Art of IC Testing , 1997, IEEE Des. Test Comput..

[8]  Charles E. Molnar,et al.  Anomalous Behavior of Synchronizer and Arbiter Circuits , 1973, IEEE Transactions on Computers.

[9]  H. C. Brearley ILLIAC II-A Short Description and Annotated Bibliography , 1965, IEEE Trans. Electron. Comput..

[10]  Huey Ling High Speed Binary Adder , 1981, IBM J. Res. Dev..

[11]  Theodore I. Kamins,et al.  Device Electronics for Integrated Circuits , 1977 .

[12]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[13]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[14]  Leslie Berlin,et al.  The Man Behind the Microchip: Robert Noyce and the Invention of Silicon Valley , 2005 .

[15]  Bob Bentley,et al.  Validating the Intel(R) Pentium(R) 4 microprocessor , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[16]  G. Boole An Investigation of the Laws of Thought: On which are founded the mathematical theories of logic and probabilities , 2007 .

[17]  Doron D. Swade The construction of Charles Babbage's Difference Engine No. 2 , 2005, IEEE Annals of the History of Computing.

[18]  Kiyoshi Oguri,et al.  Asynchronous Circuit Design , 2001 .

[19]  Werner Buchholz,et al.  Planning a Computer System: Project Stretch , 1962 .

[20]  Michael J. Flynn,et al.  Advanced Computer Arithmetic Design , 2001 .

[21]  David A. Wood,et al.  A Primer on Memory Consistency and Cache Coherence , 2012, Synthesis Lectures on Computer Architecture.

[22]  John Mick,et al.  Bit-slice Microprocessor Design , 1980 .

[23]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[24]  Hung-Hsiang Jonathan Chao,et al.  Behavior analysis of CMOS D flip-flops , 1989 .

[25]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[26]  Emmett Kilgariff,et al.  Fermi GF100 graphics processing unit (GPU) , 2010, 2010 IEEE Hot Chips 22 Symposium (HCS).

[27]  Zvonko G. Vranesic,et al.  Fundamentals of Digital Logic with VHDL Design , 2008 .

[28]  George H. Mealy,et al.  A method for synthesizing sequential circuits , 1955 .

[29]  B. Ramakrishna Rau,et al.  Pseudo-randomly interleaved memory , 1991, ISCA '91.

[30]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[31]  EDWARD J. McCLUSKEY,et al.  Fault Equivalence in Combinational Logic Networks , 1971, IEEE Transactions on Computers.

[32]  D. Huffman A Method for the Construction of Minimum-Redundancy Codes , 1952 .

[33]  Vishwani D. Agrawal,et al.  Test Generation for MOS Circuits Using D-Algorithm , 1983, 20th Design Automation Conference Proceedings.

[34]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[35]  Claude E. Shannon,et al.  A symbolic analysis of relay and switching circuits , 1938, Transactions of the American Institute of Electrical Engineers.

[36]  Allan G. Bromley Charles Babbage's Analytical Engine, 1838 , 1982 .

[37]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[38]  M. G. Lloyd Uniform Traffic Signs, Signals, and Markings , 1927 .

[39]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[40]  Niraj K. Jha,et al.  Switching and Finite Automata Theory , 2010 .

[41]  Milos D. Ercegovac,et al.  Digital Arithmetic , 2003, Wiley Encyclopedia of Computer Science and Engineering.

[42]  Resve Saleh,et al.  Analysis and Design of Digital Integrated Circuits , 1983 .

[43]  William J. Dally,et al.  Digital systems engineering , 1998 .

[44]  John Vincent Atanasoff Advent of Electronic Digital Computing , 1984, Annals of the History of Computing.

[45]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[46]  E. Wright,et al.  An Introduction to the Theory of Numbers , 1939 .

[47]  Yao-Wen Chang,et al.  Timing modeling and optimization under the transmission line model , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[48]  Dilip K. Bhavsar An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264 , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[49]  M. Karnaugh The map method for synthesis of combinational logic circuits , 1953, Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics.

[50]  KOZO KINOSHITA,et al.  Built-In Testing of Memory Using an On-Chip Compact Testing Scheme , 1984, IEEE Transactions on Computers.

[51]  Fabrizio Petrini,et al.  Cell Multiprocessor Communication Network: Built for Speed , 2006, IEEE Micro.

[52]  Stephen H. Unger The essence of logic circuits , 1989 .

[53]  William J. Dally,et al.  The GPU Computing Era , 2010, IEEE Micro.

[54]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[55]  Uming Ko,et al.  High-performance energy-efficient D-flip-flop circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[56]  H. Olson,et al.  Electronic Music Synthesizer , 1955 .

[57]  David Harris,et al.  A taxonomy of parallel prefix networks , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[58]  Stuart F. Oberman,et al.  A seventh-generation x86 microprocessor , 1999 .

[59]  Tracy Kidder,et al.  Soul of a New Machine , 1981 .

[60]  Randal E. Bryant MOSSIM: A Switch-Level Simulator for MOS LSI , 1981, 18th Design Automation Conference.

[61]  H. Arnold,et al.  Ford Methods and the Ford Shops , 1972 .

[62]  David H. Bailey,et al.  Vector Computer Memory Bank Contention , 1987, IEEE Transactions on Computers.

[63]  Fred P. Brooks,et al.  The Mythical Man-Month , 1975, Reliable Software.

[64]  Leslie Berlin,et al.  The Man Behind the Microchip: Robert Noyce and the Invention of Silicon Valley , 2005 .

[65]  Frederick P. Brooks,et al.  The Mythical Man-Month: Essays on Softw , 1978 .

[66]  I. Sutherland,et al.  Logical Effort: Designing Fast CMOS Circuits , 1999 .

[67]  P.M. Russo,et al.  Microprocessors in consumer products , 1978, Proceedings of the IEEE.

[68]  E. W. Veitch,et al.  A chart method for simplifying truth functions , 1952, ACM '52.

[69]  Joseph Cavanagh,et al.  Computer Arithmetic and Verilog HDL Fundamentals , 2009 .

[70]  Frank O’Brien The Apollo Guidance Computer , 2010 .

[71]  Samir Palnitkar,et al.  Verilog HDL , 2003 .

[72]  Stephen S. Yau,et al.  An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits , 1971, IEEE Transactions on Computers.

[73]  Norman P. Jouppi,et al.  MIPS: A microprocessor architecture , 1982, MICRO 15.

[74]  Stephen Bristow The History of Video Games , 1977, IEEE Transactions on Consumer Electronics.

[75]  Peter J. Ashenden,et al.  The Designer's Guide to VHDL , 1995 .

[76]  Bruce Jacob,et al.  Memory Systems: Cache, DRAM, Disk , 2007 .

[77]  Carver A. Mead,et al.  Minimum propagation delays in VLSI , 1982 .

[78]  Frank O'Brien The Apollo Guidance Computer: Architecture and Operation , 2010 .

[79]  Wayne Nelson,et al.  Analysis of Accelerated Life Test Data - Part I: The Arrhenius Model and Graphical Methods , 1971, IEEE Transactions on Electrical Insulation.

[80]  J. L. Smith,et al.  A One-Microsecond Adder Using One-Megacycle Circuitry , 1956, IRE Trans. Electron. Comput..

[81]  Mathias Beike,et al.  Digital Integrated Circuits A Design Perspective , 2016 .

[82]  M. V. Wilkes,et al.  Micro-programming and the design of the control circuits in an electronic digital computer , 1953 .

[83]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[84]  O. L. Macsorley High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[85]  Donald J. Patterson,et al.  Computer organization and design: the hardware-software interface (appendix a , 1993 .

[86]  David A. Huffman,et al.  The synthesis of sequential switching circuits , 1954 .

[87]  Douglas W. Stout,et al.  Boundary-scan design principles for efficient LSSD ASIC testing , 1990 .

[88]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[89]  Mark Horowitz,et al.  Timing Models for MOS Circuits , 1983 .

[90]  Erik Brunvand,et al.  Digital VLSI Chip Design with Cadence and Synopsys CAD Tools , 2009 .

[91]  G. A. Montgomerie,et al.  Sketch for an algebra of relay and contactor circuits , 1948 .

[92]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[93]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[94]  William J. Dally,et al.  The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer , 2010, 2010 IEEE Symposium on Asynchronous Circuits and Systems.

[95]  E. McCluskey Minimization of Boolean functions , 1956 .

[96]  Anoop Gupta,et al.  Parallel computer architecture - a hardware / software approach , 1998 .

[97]  David J. Kuck,et al.  The Burroughs Scientific Processor (BSP) , 1982, IEEE Transactions on Computers.