ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs

3-D NAND flash is one of the most prospective advances in flash memory industry. While 3-D flash improves cell density and reduces lithography cost through die stacking, it suffers from severe program disturbance, which leads to significant performance and lifetime degradation for 3-D flash-based SSDs. To address the above challenge, we propose ApproxFTL, an approximate-write aware flash translation layer design, that uses approximate-write operations to store error-resilient data of modern applications. By reducing the maximal threshold voltage and tightening the guard bands between multilevel cell states, approximate write operations not only finish early but also exhibit large disturbance reduction, which can be exploited to alleviate disturbance in physical blocks that save both precise and approximate data. ApproxFTL maximizes the disturbance mitigation through approximate-write aware data placement, wear leveling, and garbage collection enhancements. Our experimental results show that ApproxFTL, while preserving high data quality, improves the read and write response time of flash accesses by 41.38% and 45.64% on average, respectively, and extends the lifetime of 3-D flash-based SSDs by 5.75% when comparing to the state-of-the-art.

[1]  Young-Woo Park,et al.  An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  Dan Grossman,et al.  EnerJ: approximate data types for safe and general low-power computation , 2011, PLDI '11.

[3]  Shih-Hung Chen,et al.  Overview of 3D NAND Flash and progress of vertical gate (VG) architecture , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

[4]  Chih-Yuan Lu,et al.  Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage , 2013, 2013 Symposium on VLSI Technology.

[5]  J. Kessenich,et al.  Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[6]  Chih-Yuan Lu,et al.  Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND , 2016, IEEE Transactions on Electron Devices.

[7]  Xin Xu,et al.  Exploring Data-Level Error Tolerance in High-Performance Solid-State Drives , 2015, IEEE Transactions on Reliability.

[8]  Shih-Hung Chen,et al.  A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[9]  Tei-Wei Kuo,et al.  On relaxing page program disturbance over 3D MLC flash memory , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[10]  Youngjae Kim,et al.  DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.

[11]  Song Liu,et al.  Flikker: saving DRAM refresh-power through critical data partitioning , 2011, ASPLOS XVI.

[12]  Steven Swanson,et al.  The Harey Tortoise: Managing Heterogeneous Write Performance in SSDs , 2013, USENIX Annual Technical Conference.

[13]  Yuval Cassuto,et al.  NAND flash architectures reducing write amplification through multi-write codes , 2014, 2014 30th Symposium on Mass Storage Systems and Technologies (MSST).

[14]  Scott A. Mahlke,et al.  Rumba: An online quality management system for approximate computing , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[15]  Hong Jiang,et al.  Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity , 2011, ICS '11.

[16]  Da-Wei Chang,et al.  ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation , 2011, IEEE Transactions on Computers.

[17]  Onur Mutlu,et al.  Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[18]  Tian Luo,et al.  CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives , 2011, FAST.

[19]  Nikil D. Dutt,et al.  A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Jongmoo Choi,et al.  Advanced DC-SF Cell Technology for 3-D NAND Flash , 2013, IEEE Transactions on Electron Devices.

[21]  Eitan Yaakobi,et al.  Write Once, Get 50% Free: Saving SSD Erase Costs Using WOM Codes , 2015, FAST.

[22]  Tei-Wei Kuo,et al.  A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory , 2016, 2016 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[23]  Jacob Nelson,et al.  Approximate storage in solid-state memories , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[24]  Xavier Jimenez,et al.  Wear unleveling: improving NAND flash lifetime by balancing page endurance , 2014, FAST.

[25]  Onur Mutlu,et al.  Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation , 2013, ICCD.

[26]  Onur Mutlu,et al.  Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[27]  Sungjin Lee,et al.  Improving NAND Endurance by Dynamic Program and Erase Scaling , 2013, HotStorage.

[28]  Wook-Ghee Hahn,et al.  7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[29]  Luis Ceze,et al.  Architecture support for disciplined approximate programming , 2012, ASPLOS XVII.

[30]  Henrique S. Malvar,et al.  Approximate Storage of Compressed and Encrypted Videos , 2017, ASPLOS.

[31]  Dan Feng,et al.  Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation , 2010, 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST).

[32]  Song Jiang,et al.  Heating Dispersal for Self-Healing NAND Flash Memory , 2017, IEEE Transactions on Computers.

[33]  Jeong-Don Ihm,et al.  256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers , 2017, IEEE Journal of Solid-State Circuits.

[34]  Tei-Wei Kuo,et al.  Disturbance Relaxation for 3D Flash Memory , 2016, IEEE Transactions on Computers.

[35]  Edwin Hsing-Mean Sha,et al.  Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[36]  Tei-Wei Kuo,et al.  A light-weighted software-controlled cache for PCM-based main memory systems , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[37]  Kaushik Roy,et al.  Analysis and characterization of inherent application resilience for approximate computing , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[38]  Yoondong Park,et al.  Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage , 2006, 2009 Symposium on VLSI Technology.

[39]  Tong Zhang,et al.  Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance , 2011, FAST.

[40]  Tao Jiang,et al.  Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[41]  Y. Iwata,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[42]  Jingtong Hu,et al.  Image-Content-Aware I/O Optimization for Mobile Virtualization , 2016, ACM Trans. Embed. Comput. Syst..

[43]  Jae-Duk Lee,et al.  Effects of floating-gate interference on NAND flash memory cell operation , 2002, IEEE Electron Device Letters.

[44]  Dongkun Shin,et al.  ComboFTL: Improving performance and lifespan of MLC flash memory using SLC flash buffer , 2010, J. Syst. Archit..

[45]  Jongmoo Choi,et al.  WARM: Improving NAND flash memory lifetime with write-hotness aware retention management , 2015, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST).

[46]  Renhai Chen,et al.  DHeating: Dispersed heating repair for self-healing NAND flash memory , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[47]  Dong-Ho Lee,et al.  HFTL: hybrid flash translation layer based on hot data identification for flash memory , 2009, IEEE Transactions on Consumer Electronics.

[48]  Liang Shi,et al.  Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[49]  Henrique S. Malvar,et al.  High-Density Image Storage Using Approximate Memory Cells , 2016, ASPLOS.

[50]  Li-Pin Chang,et al.  Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs , 2008, 2008 Asia and South Pacific Design Automation Conference.

[51]  Chong Leong Gan,et al.  3D Flash Memories , 2016, Microelectron. Reliab..