A 60-GHz CMOS receiver with an on-chip ADC

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is −38.5 dBm.

[1]  Mikko Kärkkäinen,et al.  Millimeter-Wave Integrated Circuits in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[2]  Ali M. Niknejad,et al.  A Robust 24mW 60GHz Receiver in 90nm Standard CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3]  I. Seto,et al.  A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer , 2008, IEEE Journal of Solid-State Circuits.

[4]  Saska Lindfors,et al.  A WiMedia UWB receiver with a synthesizer , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

[5]  Behzad Razavi,et al.  A 60GHz CMOS Receiver Using a 30GHz LO , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.