A simultaneous, radix four, I2L multiplier mechanized via repeated addition

The design of a radix 4 simultaneous multiplier, utilizing I<supscrpt>2</supscrpt>L circuits, is presented. Because of the relative efficiency of threshold logic implementations in I<supscrpt>2</supscrpt>L to those using logic primitives, the multiplication is implemented by adding together copies of the multiplicand. This is shown to be more efficient than generating and summing single position partial products. The radix 4 design is also compared to an equivalent radix 2 multiplier (also mechanized with I<supscrpt>2</supscrpt>L circuits), and is shown to be faster and less costly in terms of required chip area.

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