Communication-centric debug of systems-on-chip using networks-on-chip

This report explores the possibilities of combining debug methodologies and communication-centric design using NoCs. It also describes an implementation of a debug architecture for the Philips AEthereal NoC, which is fully integrated in the AEthereal design flow.

[1]  Axel Jantsch,et al.  Will Networks on Chip Close the Productivity Gap? , 2003, Networks on Chip.

[2]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[3]  Kees G. W. Goossens,et al.  An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  Fenguangzhai Song.  CD , 1992 .

[5]  Kees Goossens,et al.  Concepts and Implementation of the Philips Network-on-Chip , 2003 .

[6]  Axel Jantsch,et al.  Networks on chip , 2003 .

[7]  Kees G. W. Goossens,et al.  Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[8]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[9]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[10]  Bart Vermeulen,et al.  Test and debug strategy of the PNX8525 Nexperia/sup TM/ digital video platform system chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Ran Ginosar,et al.  Cost considerations in network on chip , 2004, Integr..

[12]  Kees G. W. Goossens,et al.  Networks on silicon: blessing or nightmare? , 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.

[13]  B. Vermeulen,et al.  Core-based scan architecture for silicon debug , 2002, Proceedings. International Test Conference.

[14]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[15]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[16]  Kees G. W. Goossens,et al.  An event-based network-on-chip monitoring service , 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

[17]  Kees G. W. Goossens,et al.  Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective , 2006, 2006 International Symposium on Industrial Embedded Systems.

[18]  Kees G. W. Goossens,et al.  Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..

[19]  Kees G. W. Goossens,et al.  NoC monitoring: impact on the design flow , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[20]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .