Analytical modeling and evaluation of network-on-chip architectures

Network-on-chip (NoC) architectures adopted for System-on-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, and silicon area requirements. Evaluating NoC architectures is usually performed using simulations which provide little insight on how different design parameters affect the actual NoC performance metrics. Analytical models that allow rapid trade-off investigations of NoC parameters and accelerate the estimation of main metrics are required. In this paper, a Network Calculus-based methodology is presented to analyze and evaluate the performance metrics such as the latency and the cost metrics such as the energy consumption of NoC-based architectures. The WK-recursive on-chip interconnect is analyzed and results are compared against those produced using simulations. The values obtained by simulations and by analysis show the same increasing/decreasing trends in the same order of magnitude.

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