A 32 /spl times/ 32 cellular test chip targeting new functionalities

In this paper the design of a cellular computer with 32/spl times/32 cells is discussed by referencing to different points of alternatives for realizing massively parallel analogue processor arrays. The design is a combination of cellular nonlinear network type computing and an analog microprocessor. Motivations are given for the selected solutions that are used to implement a test chip with a resolution of 32/spl times/32 cells. Digital solutions are used in the 32/spl times/32 design to mitigate the effect of traditional bottlenecks in computing speed, namely analog weight programming and analog I/O. Furthermore, as A/D/A converters are included in each cell, alternative solutions for analog storage are highlighted.

[1]  A. Paasio,et al.  Implementing grayscale morphological operators with a compact ranked order extractor circuit , 2002, Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications.

[2]  Saska Lindfors,et al.  A cellular nonlinear network for digital error correction , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[3]  Kari Halonen,et al.  A QCIF Resolution Binary I/O CNN-UM Chip , 1999, J. VLSI Signal Process..

[4]  Fausto Sargeni,et al.  A 6 × 6 Cells Interconnection-Oriented Programmable Chip for CNN , 1998 .

[5]  Kari Halonen,et al.  A Compact Computational Core for Image Processing , 2001 .

[6]  A. Rodriguez-Vazquez,et al.  A CMOS analog parallel array processor chip with programmable dynamics for early vision tasks , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[7]  Tamás Roska,et al.  CNN‐based difference‐controlled adaptive non‐linear image filters , 1998 .

[8]  Jan-Erik Eklund,et al.  VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Kari Halonen,et al.  An analog array processor hardware realization with multiple new features , 2002, Proceedings of the 2002 International Joint Conference on Neural Networks. IJCNN'02 (Cat. No.02CH37290).

[10]  Leon O. Chua,et al.  Programmable analogue vlsi cnn chip with local digital logic , 1992, Int. J. Circuit Theory Appl..

[11]  G. Linan,et al.  ACE16K: An advanced focal-plane analog programmable array processor , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[12]  Tamás Roska,et al.  The CNN universal machine: an analogic array computer , 1993 .

[13]  Fausto Sargeni,et al.  A 6 x 6 Cells Interconnection-Oriented Programmable Chip for CNN , 1998 .