Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC

Non-linear voltage-to-frequency characteristic of a voltage-controlled oscillator (VCO) severely curtails the dynamic range of analog-to-digital converters (ADCs) built with VCOs. Typical approaches to enhance the dynamic range include embedding the VCO-based ADC in a ΔΣ loop or to post-process the digital data for calibration, both of which impose significant power constraints. In contrast, in this work the VCO-based ADC is linearized through a filtered dithering technique, wherein the VCO-based ADC is used as a fine stage that processes the residue from a coarse stage in a 0-1 MASH structure. The proposed filtered dithering technique conditions the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO nonlinearity. The work resorts to multiple other signal processing techniques to build a high-resolution, wideband prototype, in 65 nm complementary metal-oxide semiconductor (CMOS), that achieves 10 effective number of bits (ENOB) in digitizing signals with 50 MHz bandwidth consuming 8.2 mW at a figure of merit (FoM) of 90 fJ/conv.step.

[1]  I. Galton,et al.  A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR , 2000, IEEE Journal of Solid-State Circuits.

[2]  Pavan Kumar Hanumolu,et al.  A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Siamak Delshadpour,et al.  A Spur Elimination Technique for Phase Interpolation-Based Fractional-$N$ PLLs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Sudhakar Pamarti,et al.  Filtering of subtractive discrete dither in quantizers: Some new results , 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

[5]  Amr Elshazly,et al.  A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[6]  Michiel Steyaert,et al.  A 0.02mm2 65nm CMOS 30MHz BW all-digital differential VCO-based ADC with 64dB SNDR , 2010, 2010 Symposium on VLSI Circuits.

[7]  I. Galton,et al.  A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.

[8]  Kok Lim Chan,et al.  A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquilst band , 2007, 2007 IEEE Symposium on VLSI Circuits.

[9]  Ian Galton,et al.  A mostly digital variable-rate continuous-time ADC ΔΣ modulator , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[10]  Pavan Kumar Hanumolu,et al.  A Deterministic Digital Background Calibration Technique for VCO-Based ADCs , 2014, IEEE Journal of Solid-State Circuits.

[11]  Abhishek Ghosh.  Signal Processing Techniques EnablingWideband A/D Converters , 2013 .

[12]  Y. Lim,et al.  FIR filter design over a discrete powers-of-two coefficient space , 1983 .

[13]  Sudhakar Pamarti,et al.  Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta–Sigma Modulators , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Bernard C. Levy.  A Study of Subtractive Digital Dither in Single-Stage and Multi-Stage Quantizers , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  R. Gray,et al.  Dithered Quantizers , 1993, Proceedings. 1991 IEEE International Symposium on Information Theory.

[16]  Behzad Razavi,et al.  A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate , 2014, IEEE J. Solid State Circuits.

[17]  Ian Galton.  Spectral shaping of circuit errors in digital-to-analog converters , 1997 .

[18]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[19]  B. Razavi,et al.  A 10-Bit 500-MS/s 55-mW CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[20]  J.E. Franca,et al.  A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-/spl mu/ hboxm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[21]  Ian Galton.  Digital cancellation of D/A converter noise in pipelined A/D converters , 2000 .

[22]  L. Liu,et al.  A 95dB SNDR audio ΔΣ modulator in 65nm CMOS , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[23]  M.Z. Straayer,et al.  A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer , 2008, IEEE Journal of Solid-State Circuits.

[24]  M.H. Perrott,et al.  A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[25]  Michael H. Perrott,et al.  A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time � ADC With VCO-Based Integrator and Quantizer Implemented in 0 . 13 � m CMOS , 2009 .

[26]  Kok Lim Chan,et al.  Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Ian Galton,et al.  A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB , 2013, IEEE Journal of Solid-State Circuits.

[28]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[29]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[30]  John G. Kauffman,et al.  An 8.5 mW Continuous-Time $\Delta \Sigma $ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR , 2011, IEEE Journal of Solid-State Circuits.

[31]  Andreas Kaiser,et al.  Input switch configuration suitable for rail-to-rail operation of switched-opamp circuits , 1999 .

[32]  John Vanderkooy,et al.  Quantization and Dither: A Theoretical Survey , 1992 .

[33]  D.A. Johns,et al.  A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator , 2009, IEEE Journal of Solid-State Circuits.

[34]  Amr Elshazly,et al.  A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer , 2012, IEEE Journal of Solid-State Circuits.

[35]  B. Razavi,et al.  An 8-bit 150-MHz CMOS A/D converter , 1999, IEEE Journal of Solid-State Circuits.

[36]  Jaewook Kim,et al.  Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[37]  A. Sripad,et al.  A necessary and sufficient condition for quantization errors to be uniform and white , 1977 .

[38]  Ian Galton,et al.  A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC , 2010, IEEE Journal of Solid-State Circuits.

[39]  Sudhakar Pamarti,et al.  A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.