구성형 프로세서의 성능 향상을 위한 Pseudo-VLIW 구조

RISC-based configurable processor usually stalls the base processor part when executing the auxiliary data path added for an ISE (Instruction-Set Extension). In this paper, we suggest a novel micro-architecture which we call pseudo-VLIW architecture. It can execute the data path for ISEs and the base processor part concurrently by adding minimal hardware. An experiment with the pseudo-VLIW architecture shows 62% performance improvement.