Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure

The VLSI structure design method includes shift adding technology to converting the multiplication operation in the filter into shift register and adder operation to reduce the operation amount save hardware spending greatly; buffering technology to connect row and line filters for concurrent performing to save memory space; delay register technology for streamline processing to speed hardware processing and raise hardware utilization; and united symmetrical expanding technology to raise the versatility of the present invention. The present invention is one efficient 2D DWT hardware scheme with several advantages. Through the optimized design of row filter and line filter for 2D discrete wavelet conversion, the hardware utilization is made to reach 100 %, there are two outputs within one work clock, parallel processing is realized without increasing hardware spending, and the obtained hardware structure is simple and easy to realize with VLSI.