System design of a CC-NUMA multiprocessor architecture using formal specification, model-checking, co-simulation, and test generation

Abstract.The application of formal methods to the system-level design of hardware components is still an open issue for which concrete case-studies are needed. We present here an industrial experiment concerning the application of the process algebraic language lotos (iso standard 8807) to the design of polykid, a cc-numa (cache coherent – non-uniform memory access ) multiprocessor architecture developed by bull. The formal descriptions developed for polykid have served as a basis not only for model-checking verification using cadp (caesar/aldebaran development package), but also for hardware-software co-simulation using the exec/caesartool, and for automatic generation of executable tests using the tgv tool.

[1]  Alan J. Hu,et al.  Formal verification of the HAL S1 System cache coherence protocol , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[2]  Laurent Mounier,et al.  Compositional State Space Generation from Lotos Programs , 1997, TACAS.

[3]  Tommaso Bolognesi,et al.  Tableau methods to describe strong bisimilarity on LOTOS processes involving pure interleaving and enabling , 1994, FORTE.

[4]  César Viho,et al.  An Industrial Experiment in Automatic Generation of Executable Test Suites for a Cache Coherency Protocol , 1998, IWTCS.

[5]  David L. Dill,et al.  Automatic verification of the SCI cache coherence protocol , 1995, CHARME.

[6]  Luigi Logrippo,et al.  Specifying Hardware Systems in LOTOS , 1993, CHDL.

[7]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[8]  Eric Dubuis,et al.  An Algorithm for Translating LOTOS Behavior Expressions into Automata and Ports , 1989, FORTE.

[9]  Anoop Gupta,et al.  The directory-based cache coherence protocol for the DASH multiprocessor , 1990, ISCA '90.

[10]  David Park,et al.  Concurrency and Automata on Infinite Sequences , 1981, Theoretical Computer Science.

[11]  Srivatsan Srinivasan,et al.  Formal verification of a snoop-based cache coherence protocol using symbolic model checking , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[12]  Iso. Lotos,et al.  A Formal Description Technique Based on the Temporal Ordering of Observational Behaviour , 1985 .

[13]  Tomás de Miguel,et al.  From LOTOS to C , 1988, FORTE.

[14]  Hartmut Ehrig,et al.  Fundamentals of Algebraic Specification 1: Equations and Initial Semantics , 1985 .

[15]  Luciano Lavagno,et al.  Models of computation for system design , 2000 .

[16]  Ásgeir Th. Eiríksson The Formal Design of 1M-gate ASICs , 2000, Formal Methods Syst. Des..

[17]  Thierry Jéron,et al.  An Experiment in Automatic Generation of Test Suites for Protocols with Verification Technology , 1997, Sci. Comput. Program..

[18]  Joseph Sifakis,et al.  Compilation and verification of LOTOS specifications , 1990, PSTV.

[19]  Kenneth J. Turner,et al.  Using Formal Description Techniques: An Introduction to Estelle, Lotos, and SDL , 1993 .

[20]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[21]  Ásgeir Th. Eiríksson The Formal Design of 1M-gate ASICs , 1998, FMCAD.

[22]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[23]  Anna Philippou,et al.  Tools and Algorithms for the Construction and Analysis of Systems , 2018, Lecture Notes in Computer Science.

[24]  Nadia Tawbi,et al.  Specification and Verification of the PowerScaleTM Bus Arbitration Protocol: An Industrial Experiment with LOTOS , 1996, FORTE.

[25]  Amy P. Felty,et al.  Protocol Verification in Nuprl , 1998, CAV.

[26]  Robin Milner,et al.  A Calculus of Communicating Systems , 1980, Lecture Notes in Computer Science.

[27]  Son T. Vuong,et al.  Introduction to Algebraic Specifications Based on the Language ACT ONE , 1992, Comput. Networks ISDN Syst..

[28]  Kenneth J. Turner,et al.  Verifying and Testing Asynchronous Circuits using LOTOS , 2000, FORTE.

[29]  Hubert Garavel,et al.  Compilation of LOTOS Abstract Data Types , 1989, FORTE.

[30]  Nicolas Halbwachs,et al.  Synchronous Programming of Reactive Systems , 1992, CAV.

[31]  Ganesh Gopalakrishnan,et al.  Deriving Efficient Cache Coherence Protocols Through Refinement , 1998, Formal Methods Syst. Des..

[32]  Thierry Jéron,et al.  Using On-The-Fly Verification Techniques for the Generation of test Suites , 1996, CAV.

[33]  Andrew Seawright,et al.  Modeling and synthesis of behavior, control and data flow , 2000 .

[34]  David B. Gustavson,et al.  Scalable Coherent Interface , 1990, COMPEURO'90: Proceedings of the 1990 IEEE International Conference on Computer Systems and Software Engineering@m_Systems Engineering Aspects of Complex Computerized Systems.

[35]  Richard O. Sinnott,et al.  DILL: Specifying Digital Logic in LOTOS , 1993, FORTE.

[36]  Laurent Mounier,et al.  A Tool Set for deciding Behavioral Equivalences , 1991, CONCUR.

[37]  M. Yoeli,et al.  Title of Paper : Examples of LOTOS − Based Verification of Asynchronous Circuits , 2022 .

[38]  Thomas A. Henzinger,et al.  Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems , 1999, CAV.

[39]  Michel Dubois,et al.  Verification techniques for cache coherence protocols , 1997, CSUR.

[40]  Somesh Jha,et al.  Verification of the Futurebus+ cache coherence protocol , 1993, Formal Methods Syst. Des..

[41]  Peter Sjödin From LOTOS specifications to distributed implementations , 1992 .

[42]  Hubert Garavel,et al.  OPEN/CÆSAR: An OPen Software Architecture for Verification, Simulation, and Testing , 1998, TACAS.

[43]  David L. Dill,et al.  Verification of Cache Coherence Protocols by Aggregation of Distributed Transactions , 1998, Theory of Computing Systems.