Analytical estimation of signal transition activity from word-level statistics
暂无分享,去创建一个
Naresh R. Shanbhag | Ibrahim N. Hajj | Sumant Ramprasad | Naresh R Shanbhag | S. Ramprasad | I. Hajj
[1] Kiyoo Itoh,et al. Sub-1-V swing internal bus architecture for future low-power ULSIs , 1993 .
[2] H. Samueli,et al. An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients , 1989 .
[3] Peter No,et al. Digital Coding of Waveforms , 1986 .
[4] Radu Marculescu,et al. Switching activity analysis considering spatiotemporal correlations , 1994, ICCAD.
[5] Keshab K. Parhi,et al. Synthesis of control circuits in folded pipelined DSP architectures , 1992 .
[6] Kurt Keutzer,et al. Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[7] Eric A. Vittoz,et al. Low-power design: ways to approach the limits , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[8] Farid N. Najm,et al. Towards a high-level power estimation capability [digital ICs] , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Keshab K. Parhi,et al. Algorithm transformation techniques for concurrent processors , 1989, Proc. IEEE.
[10] Farid N. Najm,et al. Towards a high-level power estimation capability , 1995, ISLPED '95.
[11] M. Horowitz,et al. Low-power digital design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.
[12] John G. Proakis,et al. Probability, random variables and stochastic processes , 1985, IEEE Trans. Acoust. Speech Signal Process..
[13] Jan M. Rabaey,et al. Activity-sensitive architectural power analysis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] Marios C. Papaefthymiou,et al. Precomputation-based sequential logic optimization for low power , 1994, ICCAD '94.
[15] Farid N. Najm,et al. A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[16] Sujit Dey,et al. Glitch analysis and reduction in register transfer level power optimization , 1996, DAC '96.
[17] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[18] Robert H. Dennard,et al. CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.
[19] An-Chang Deng,et al. The design and implementation of PowerMill , 1995, ISLPED '95.
[20] Naresh R. Shanbhag. A fundamental basis for power-reduction in VLSI circuits , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[21] I. Miller. Probability, Random Variables, and Stochastic Processes , 1966 .
[22] Maurice Bellanger,et al. Adaptive digital filters and signal analysis , 1987 .
[23] Kaushik Roy,et al. Estimation of circuit activity considering signal correlations and simultaneous switching , 1994, ICCAD '94.
[24] Farid N. Najm,et al. Transition density: a new measure of activity in digital circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[25] Farid N. Najm,et al. Power macromodeling for high level power estimation , 1997, DAC.
[26] Chi-Ying Tsui,et al. Efficient estimation of dynamic power consumption under a real delay model , 1993, ICCAD.
[27] Miodrag Potkonjak,et al. Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[28] Keshab K. Parhi,et al. HEAT: hierarchical energy analysis tool , 1996, DAC '96.
[29] Bhaskar Sinha,et al. High-speed recursive digital filter realization , 2017 .
[30] K. H. Barratt. Digital Coding of Waveforms , 1985 .
[31] K. Keutzer,et al. On average power dissipation and random pattern testability of CMOS combinational logic networks , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[32] Nestoras Tzartzanis,et al. Low-power digital systems based on adiabatic-switching principles , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[33] Luca Benini,et al. Automatic synthesis of low-power gated-clock finite-state machines , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[34] A. W. M. van den Enden,et al. Discrete Time Signal Processing , 1989 .
[35] Kurt Keutzer,et al. On average power dissipation and random pattern testability of CMOS combinational logic networks , 1992, ICCAD.
[36] Jan M. Rabaey,et al. Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[37] R. Marculescu,et al. Switching Activity Analysis Considering Spatioternporal Correlations , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[38] B. Atal,et al. Predictive coding of speech signals and subjective error criteria , 1979 .