A 600-MSPS 8-bit CMOS ADC Using Distributed Track-and-Hold With Complementary Resistor/Capacitor Averaging

An 8-bit 600 megasamples-per-second (MSPS) analog-to-digital converter (ADC) has been implemented in 0.18-mum CMOS to achieve a minimum signal-to-noise-and-distortion ratio (SNDR) of 40 dB and a spurious-free dynamic range (SFDR) of 45 dB with input-signal bandwidth up to 200 MHz. The ADC is also capable of sampling up to 1 gigasamples/s and maintaining 39-dB SNDR at an input-signal frequency of 55 MHz. Distributed track-and-hold (DT&H) is employed at the ADC front end to relieve the linearity burden on individual T&H subunit. Complementary resistor and capacitor averaging networks are employed before and after DT&H switches separately in order to alleviate offset- and switching-induced errors, respectively. The fabricated ADC occupies 0.5 mm2 in chip area and consumes 207 mW from a 1.8-V supply.

[1]  S. Pavan,et al.  A Distortion Compensating Flash Analog-to-Digital Conversion Technique , 2006, IEEE Journal of Solid-State Circuits.

[2]  Hui Pan,et al.  A 600 MSPS 8-bit folding ADC in 0.18 /spl mu/m CMOS , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[3]  K. Bult,et al.  An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2 , 1997, IEEE J. Solid State Circuits.

[4]  A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  Asad A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS , 2001 .

[6]  Andrea Boni,et al.  Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Gabor C. Temes,et al.  Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Hui Pan,et al.  Spatial filtering in flash A/D converters , 2003 .

[9]  G. Geelen,et al.  An 8b 600MS/s 200mW CMOS folding A/D converter using an amplifier preset technique , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[10]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[11]  M. Vertregt,et al.  A 6b 1.6GSample/s flash ADC in 0.18/spl mu/m CMOS using averaging termination , 2002 .

[12]  A.A. Abidi,et al.  A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR , 2000, IEEE Journal of Solid-State Circuits.

[13]  K. Kattmann,et al.  A Technique For Reducing Differential Non-linearity Errors In Flash A/D Converters , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[14]  A. Matsuzawa,et al.  A 10 b 20 MHz 30 mW pipelined interpolating CMOS ADC , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[15]  A.G.W. Venes,et al.  An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[16]  Xicheng Jiang,et al.  A 2 GS/s 6 b ADC in 0.18 /spl mu/m CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..