A 50mhz Cmos Programmable Logic Device

PROGRAMMABLE LOGlC DEVICES (PLD’s) are traditionally implemented in bipolar fuse technology’. The bipolar fuse technology satisfies the speed requirement of these devices, bu t has two major disadvantages: ( 1 ) it has significantly higher power consun-,ption and, (2) the fuse technology does not allow reprogrammability and 100% testability. The power limitation of packages have prevented the bipolar designs from achieving higher levels of integration. Scaled CMOS technology, along with the demonstrated reliability and reprogrammability of FAMOS devices has been achieving bipolar performance at much lower power levels2. The low power of CMOS technology allows designers to explore the architectures which need much higher levels of integration3”.

[1]  R. Pugh,et al.  A 19ns 250mW programmable logic device , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Sau Wong,et al.  CMOS erasable programmable logic with zero standby power , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  R. Pugh,et al.  A 19-ns 250-mW CMOS erasable programmable logic device , 1986 .