Performance analysis of various scheduling algorithms using FPGA platforms

This paper discusses the synthesis and implementation of various scheduling algorithms for Network-on-Chip communication. Traditionally these scheduling algorithms were implemented on ASIC platforms generally for shared bus based interconnection systems. In this paper we carry a comparative analysis by synthesizing and implementing various scheduling algorithms for configuring the crossbar in input queued switches. The implementation is carried out using various arbitration networks responsible for scheduling 8-bit input requests. The implementation targets Spartan6 FPGA family. The analysis concludes that the scheduling algorithm based on CLA based encoding network shows lower power delay product and lower area delay product and a reasonably lower resource utilization when implemented for speed optimization goal.

[1]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[2]  Chung-Ta King,et al.  TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[3]  Nick McKeown,et al.  Scheduling algorithms for input-queued cell switches , 1996 .

[4]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[5]  Harald Michalik,et al.  SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications , 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

[6]  Akram Ben Ahmed,et al.  Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC , 2010, 2010 International Conference on Broadband, Wireless Computing, Communication and Applications.

[7]  Thomas E. Anderson,et al.  High-speed switch scheduling for local-area networks , 1993, TOCS.

[8]  Yuan Xie,et al.  LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[9]  Hoi-Jun Yoo,et al.  A distributed crossbar switch scheduler for on-chip networks , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[10]  Laxmi N. Bhuyan,et al.  An efficient packet scheduling algorithm in network processors , 2005, Proceedings IEEE 24th Annual Joint Conference of the IEEE Computer and Communications Societies..

[11]  Mark J. Karol,et al.  Queueing in high-performance packet switching , 1988, IEEE J. Sel. Areas Commun..

[12]  Jean C. Walrand,et al.  Achieving 100% throughput in an input-queued switch , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[13]  Sandip Kundu,et al.  Task model for on-chip communication infrastructure design for multicore systems , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[14]  Nick McKeown,et al.  Designing and implementing a fast crossbar scheduler , 1999, IEEE Micro.