Self-characterization of Combinatorial Circuit Delays in FPGAs
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Peter Y. K. Cheung | N. Pete Sedcole | Justin S. J. Wong | N. P. Sedcole | P. Cheung | Justin S. J. Wong
[1] Patrick Girard,et al. High quality TPG for delay faults in look-up tables of FPGAs , 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.
[2] Gordon W. Roberts,et al. A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[3] Irith Pomeranz,et al. At-speed delay testing of synchronous sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[4] Ryszard Szplet,et al. Interpolating time counter with 100 ps resolution on a single FPGA device , 2000, IEEE Trans. Instrum. Meas..
[5] Peter Y. K. Cheung,et al. Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis , 2007, FPGA '07.
[6] Charles E. Stroud,et al. BIST-Based Delay-Fault Testing in FPGAs , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).
[7] Xiao-Yu Li,et al. FPGA as Process Monitor-an effective method to characterize poly gate CD variation and its impact on product performance and yield , 2004, IEEE Transactions on Semiconductor Manufacturing.
[8] Peter Y. K. Cheung,et al. Within-die delay variability in 90nm FPGAs and beyond , 2006, 2006 IEEE International Conference on Field Programmable Technology.
[9] Cheng-Wen Wu,et al. A BIST scheme for FPGA interconnect delay faults , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).
[10] Feng Wang,et al. An effective method of characterization poly gate CD variation and its impact on product performance and yield , 2003 .
[11] Mehdi Baradaran Tahoori,et al. Application-Dependent Delay Testing of FPGAs , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Premachandran R. Menon,et al. Design-specific path delay testing in lookup-table-based FPGAs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.