Silicon-On-Insulator Technology and Devices XII

Publisher Summary Silicon on insulator (SOI) technology was conceived in the 1960s for the niche of radiation-hard circuits. A variety of SOI materials are invented in order to dielectrically separate the active device volume from the silicon substrate, using a buried oxide (BOX). The background idea is that, in a bulk silicon MOS transistor, only the superficial layer is useful for electron transport and device operation, whereas the substrate is responsible for undesirable, parasitic effects. The aim of this chapter is to overview the state-of-the-art of SOI technologies, starting with the key advantages of SOI circuits. Further describes the synthesis of the major SOI materials. The configuration and performance of typical devices are also evoked. The physical mechanisms involved in the operation of fully depleted and partially depleted SOI MOSFETs are discussed. An SOI circuit is composed of single-device islands, dielectrically isolated from each other and from the underlying substrate. The lateral isolation offers more compact design and simplified technology than in bulk-Si: there is no need of wells or inter device trenches. In addition, the vertical isolation eliminates the latch-up mechanisms that are very detrimental in bulk-Si.

[1]  Y. Horiba,et al.  Three dimensional IC for high performance image signal processor , 1987, 1987 International Electron Devices Meeting.

[2]  Sorin Cristoloveanu,et al.  Influence of series resistances and interface coupling on the transconductance of fully-depleted silicon-on-insulator MOSFETs , 1992 .

[3]  Sorin Cristoloveanu,et al.  Generation-recombination transient effects in partially depleted SOI transistors: systematic experiments and simulations , 1998 .

[4]  A. Caviglia,et al.  High voltage DMOS power FETs on thin SOI substrates , 1990, 1990 IEEE SOS/SOI Technology Conference. Proceedings.

[5]  S. Cristoloveanu.  SOI: a metamorphosis of silicon , 1999 .

[6]  E. Leobandung,et al.  A 7.9/5.5 psec room/low temperature SOI CMOS , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[7]  Gerard Ghibaudo,et al.  Analytical models of subthreshold swing and threshold voltage for thin- and ultra-thin-film SOI MOSFETs , 1990 .

[8]  D. Hisamoto,et al.  Impact of the vertical SOI 'DELTA' structure on planar device technology , 1991 .

[9]  Detailed characterization of Unibond material , 1997 .

[10]  Sorin Cristoloveanu,et al.  Hot-carrier degradation mechanisms in silicon-On-Insulator MOSFETS , 1997 .

[11]  O. Faynot,et al.  Analysis of the latch and breakdown phenomena in N and P channel thin film SOI MOSFET's as a function of temperature , 1994 .

[12]  L. T. Su,et al.  Hot-carrier effects in fully-depleted SOI nMOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[13]  Gerard Ghibaudo,et al.  Experimental investigation and numerical simulation of low‐frequency noise in thin film SOI MOSFETs , 1994 .

[14]  S. Matsumoto,et al.  An intelligent power IC with double buried-oxide layers formed by SIMOX technology , 1993 .

[15]  Chenming Hu,et al.  A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[16]  D. A. Antoniadis,et al.  Measurement and modeling of self-heating effects in SOI nMOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[17]  Moderate kink effect in fully depleted thin-film SOI MOSFETs , 1995 .

[18]  G. Baccarani,et al.  Generalized scaling theory and its application to a ¼ micrometer MOSFET design , 1984, IEEE Transactions on Electron Devices.

[19]  T. Watanabe,et al.  Elimination of bipolar-induced breakdown in fully-depleted SOI MOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[20]  Sorin Cristoloveanu,et al.  Investigation of SOI MOSFETs with ultimate thickness , 1999 .

[21]  O. Faynot,et al.  Detailed Analysis of Short-Channel SOI DT-MOSFET , 1999, 29th European Solid-State Device Research Conference.

[22]  Sorin Cristoloveanu,et al.  A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications , 2000 .

[23]  T. Tatsumi,et al.  A 60-GHz f/sub T/ super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20-Gb/s optical transmitter ICs , 1999 .

[24]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[25]  F. Balestra,et al.  Performance and physical mechanisms in deep submicron SOI MOSFETs , 1999 .

[26]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[27]  Y. Omura,et al.  An improved analytical solution of energy balance equation for short-channel SOI MOSFET's and transverse-field-induced carrier heating , 1995 .

[28]  S Cristoloveanu,et al.  Silicon films on sapphire , 1987 .

[29]  Ji-Woon Yang,et al.  1 Giga bit SOI DRAM with fully bulk compatible process and body-contacted SOI MOSFET structure , 1997 .

[30]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[31]  L. T. Su,et al.  Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's , 1994, IEEE Electron Device Letters.

[32]  R. Flaker,et al.  A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAM , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[33]  Jerry G. Fossum,et al.  Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's , 1991 .

[34]  M. Bruel.  Silicon on insulator material technology , 1995 .

[35]  Kenji Natori,et al.  Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFETs , 1990 .

[36]  Hyung-Kyu Lim,et al.  Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's , 1983, IEEE Transactions on Electron Devices.

[37]  Mansun Chan,et al.  SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films , 1995, Proceedings of International Electron Devices Meeting.

[38]  Sorin Cristoloveanu,et al.  ULTIMATE MOSFETs ON SOI: ULTRA THIN, SINGLE GATE, DOUBLE GATE, OR GROUND PLANE , 2000 .

[39]  J. Pelloie,et al.  A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs , 1998 .

[40]  Sorin Cristoloveanu,et al.  Properties of ultra-thin wafer-bonded silicon-on-insulator MOSFET's , 1991 .

[41]  S. Cristoloveanu,et al.  Recent advances in SOI materials and device technologies for high temperature , 1998, 1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132).

[42]  Gerard Ghibaudo,et al.  Analysis of the kink effect in MOS transistors , 1990 .

[43]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .