A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis

A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.

[1]  M. A. Copeland,et al.  Design and realization of a digital /spl Delta//spl Sigma/ modulator for fractional-n frequency synthesis , 1999 .

[2]  T.A. Kwasniewski,et al.  A 1.2 /spl mu/m CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[3]  Michael H. Perrott.  Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers , 1997 .

[4]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[5]  B. Miller,et al.  A multiple modulator fractional divider , 1990, 44th Annual Symposium on Frequency Control.

[6]  T. Riley,et al.  Delta-sigma modulation in fractional-N frequency synthesis , 1993 .

[7]  M.A. Copeland.  VLSI for analog/digital communications , 1991, IEEE Communications Magazine.

[8]  M. A. Copeland,et al.  A simplified continuous phase modulator technique , 1994 .

[9]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[10]  Michael H. Perrott.  Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits , 2002, DAC '02.

[11]  Michael H. Perrott,et al.  A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation , 1997, IEEE J. Solid State Circuits.

[12]  Calvin Plett,et al.  An agile ISM band frequency synthesizer with built-in GMSK data modulation , 1998, IEEE J. Solid State Circuits.

[13]  W. R. Bennett,et al.  Spectra of quantized signals , 1948, Bell Syst. Tech. J..

[14]  Calvin Plett,et al.  An interpolated frequency-hopping spread-spectrum transceiver , 1998 .

[15]  B.-S. Song,et al.  A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[16]  Gabor C. Temes,et al.  Oversampling Delta Sigma Data Converters , 1991 .

[17]  A. Sripad,et al.  A necessary and sufficient condition for quantization errors to be uniform and white , 1977 .

[18]  B. McFarland,et al.  An integrated 2.5 GHz /spl Sigma//spl Delta/ frequency synthesizer with 5 /spl mu/s settling and 2 Mb/s closed loop modulation , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[19]  D. Leeson.  A simple model of feedback oscillator noise spectrum , 1966 .