Design rules for p-i-n diode carriers sweeping in nano-rib waveguides on SOI.

In this paper we present a detailed analysis of the carrier lifetime for a p-i-n junction on silicon nano-rib waveguides. Several factors determining efficiency of carriers removal from the waveguiding region will be discussed. We compare different structure geometries and spacings between p and n doped regions to show the way to optimize electrons and holes sweeping for CW nonlinear optical devices.

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