Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees

Circuit legalization removes overlaps and keeps cell alignment with power rails while minimizing total cell displacement. Legalization is applied not only after global placement, but also after incremental optimization steps like detailed placement, gate sizing, and buffer insertion. Applying full legalization after such incremental optimizations is too time-consuming. That is why physical synthesis has been shifting from entire circuit legalization to incremental mode legalization, which keeps legality after every primitive transformation. Unfortunately, recent incremental legalization strategies employ data structures that are not suitable for handling geometric data. This work proposes a new technique that relies on an R-tree, a data structure tailored to efficient geometric data storage where objects are represented by their minimum bounding box rectangles, which allows for fast spatial queries. As compared with state-of-the-art incremental legalization algorithms, the proposed technique is at least 6 times faster and performs as many successful legalizations.

[1]  Nadine Gottschalk,et al.  Vlsi Physical Design From Graph Partitioning To Timing Closure , 2016 .

[2]  Jin Hu,et al.  Progress and Challenges in VLSI Placement Research , 2012, Proceedings of the IEEE.

[3]  Ulf Schlichtmann,et al.  Abacus: fast legalization of standard cell circuits with minimal movement , 2008, ISPD '08.

[4]  David Z. Pan,et al.  Diffusion-based placement migration , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[5]  Evangeline F. Y. Young,et al.  Cell density-driven detailed placement with displacement constraint , 2014, ISPD '14.

[6]  Guilherme Flach,et al.  Jezz: An effective legalization algorithm for minimum displacement , 2015, 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI).

[7]  Jin Hu,et al.  ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Ulrich Brenner.  VLSI legalization with minimum perturbation by iterative augmentation , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[9]  Minsik Cho,et al.  History-based VLSI legalization using network flow , 2010, Design Automation Conference.

[10]  Yih-Lang Li,et al.  Density-aware detailed placement with instant legalization , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Gi-Joon Nam,et al.  Techniques for Fast Physical Synthesis , 2007, Proceedings of the IEEE.

[12]  Andrew A. Kennings,et al.  Detailed placement accounting for technology constraints , 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

[13]  Chris C. N. Chu,et al.  The coming of age of physical synthesis , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[14]  Sandeep Koranne,et al.  Boost C++ Libraries , 2011 .

[15]  Sachin S. Sapatnekar,et al.  Handbook of Algorithms for Physical Design Automation , 2008 .