A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits

Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. The subthreshold leakage current increases exponentially in deep-submicron processes and hence is a crucial factor in scaling down designs. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, a novel technique that achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) for any CMOS complementary circuit is presented. It involves voltage balancing in the PUN and PDN paths using sleep transistors. Experimental results show significant leakage power savings (average of 54X at a temperature of 27oC) in CMOS circuits employing this sleep circuitry when compared to standard CMOS circuits. At any given temperature, using our methodology the leakage power loss increases linearly with increasing circuit complexity and hence the leakage loss can be predicted for any CMOS complementary circuit.