Interface circuit and memory system for implementing adaptive DQS latch scheme

The invention is disclosed with respect to a memory system having an interface circuit to latch the data input signal adaptively by monitoring the data strobe signal and them. The memory system as a memory device for outputting the data strobe signal and the data corresponding to the read command, the data reception of a strobe signal and output through the interface circuit to rearrange the data strobe signal to centering the edges of the data strobe signal to output data from a memory device a memory controller for latching data. The interface circuit is a data strobe signal to capture the edge of the data strobe signal according to the logic circuitry and the data strobe sampling signal for generating a plurality of select signals in response to the read command and, in response to the selection signal generating the data strobe sampling signal storing the final state machine (FSM) to rearrange the include section. Accordingly, the memory controller without the circuit configuration is complicated and power consumption is large DLL circuit configuration, monitoring the data strobe signal supplied from the memory device latches the data input signal adaptively. DLL, the memory controller, the data strobe signal, the interface circuit