A novel 5.89 bm* memory cell for 16 M-bit SRAMs has been developed. The cell is fabricated using a phase-shift photolithography which includes a new method for making 0.25 pm space patterns with the conventional stepper. To reduce cell area, the concept of small cell-ratio is also introduced. To overcome the unstable operation of the smallratio cell, an advanced polysilicon (poly-Si) PMOS transistor for load devices is used. To simultaneously obtain stable operation and extremely low stand-by power dissipation of the memory cell, a self-aligned off-set structure for the poly-Si PMOS transistor is proposed and demonstrated. An extremely small leakage current of 2-fA/cell and on/off-current ratio of 4.6 x 106 are achieved with this poly-Si PMOS transistor in a memory cell. Memory operation is also demonstrated by an experimental 32 K-bit SRAM chip. These results prove that a developed SRAM cell is promising for future 16 M-bit or higherdensity SRAMs.