ESD and latch up phenomena on advanced technology LSI

As packing density of LSI (Large Scale Integrated circuits) is increasing, device geometry has to be miniaturized. For advanced LSI such as 16-64 Mbit DRAM (dynamic random access memory), gate length of MOS (metal oxide semiconductor) transistor becomes 0.3-0.5 micron. This scaling requires thin oxide film and shallow junction. On the other hand, it is well known that the scaling causes hot carrier induced degradation. To overcome this degradation, transistor structure change to LDD (Lightly Doped Drain) or operation voltage decrease are required. However, the operation voltage decrease causes device operation error due to S/N rate decrease. Furthermore, it is popular to divide power lines between internal circuit and I/O buffer near the power pad. These improvements concerning device structure and circuit layout cause several new ESD failure phenomena and decrease of latch up immunity on CMOS (Complementary Metal Oxide Semiconductor) devices. In this paper, analysis of these new phenomena and improvement technologies are described on advanced technology devices. Furthermore, the wafer level ESD test technique is described as a new evaluation method of transistor units.