Implications of VHDL timing models on simulation and software synthesis

Abstract In this paper, we address the timing semantics of the delay models handled by VHDL. A formal model is used to characterize the runtime work required to resolve multiple assignments to signals for each of these models. Subsets of these timing models which require minimal work at runtime for resolution of multiple assignments are identified. Algorithms for generation of efficient code for simulation and synthesis in these restricted timing models are given. We present runtimes of our implementation of a simulator which uses these algorithms.