The Energy Efficiencyof IRAM Architectures

Portable systems demand energy effi ciency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficien t than conventional systems. The high density of DRAM permits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAM memory accesses to be satisfie d on-chip. Thus there is much less need to drive high-capacitance off-chip buses, which contribute significa ntly to the energy consumption of a system. To quantify this advantage we apply models of energy consumption in DRAM and SRAM memories to results from cache simulations of applications reflec tive of personal productivity tasks on low power systems. We fi nd that IRAM memory hierarchies consume as little as 22% of the energy consumed by a conventional memoryhierarchy for memoryintensive applications, while delivering comparable performance. Furthermore, the energy consumed by a system consisting of an IRAM memory hierarchy combined with an energy efficien t CPU core is as little as 40% of that of the same CPU core with a traditional memory hierarchy.