A proposal for transaction-level verification with Component Wrapper Language

We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simulation-coverage analyzer This approach combines the conventional transaction level language such as C and the signal level language based on our previously developed Component Wrapper Language (CWL). This approach is based on two concepts. The first one is a complete separation between transaction-level verification and signal-level verification for generating suitable verification suites in each design phase. The second one is the quick generation of signal-level verification suites from the original specification written in CWL. Experimental results show that our approach should yield much shorter verification periods versus conventional methods.

[1]  Carl Ramey,et al.  Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[2]  Tughrul Arslan,et al.  Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[3]  C. Norris Ip,et al.  Using Transaction-Based Verification in SystemC , 2002 .