Wide Frequency Band Characterization
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[1] J. Koomen,et al. Investigation of the MOST channel conductance in weak inversion , 1973 .
[2] Stefaan Decoutere,et al. MOSFET bias dependent series resistance extraction from RF measurements , 2003 .
[3] C. Hu,et al. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .
[4] S. Cristoloveanu,et al. New Mechanism of Body Charging in Partially Depleted SOI-MOSFETs with Ultra-thin Gate Oxides , 2002, 32nd European Solid-State Device Research Conference.
[5] Denis Flandre,et al. Substrate crosstalk reduction using SOI technology , 1997 .
[6] Denis Flandre,et al. Mobility characterization in FinFETs using split C-V technique , 2005 .
[7] Denis Flandre,et al. Substrate effect on the output conductance frequency response of SOI MOSFETs (inited paper) , 2007 .
[8] Denis Flandre,et al. Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity , 2007 .
[9] Juin J. Liou,et al. Introductory invited paper On the extraction of the source and drain series resistances of MOSFETs , 1999 .
[10] A. Caddemi,et al. Scalable and multibias high frequency modeling of multi-fin FETs , 2006 .
[11] G.J. Hu,et al. Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's , 1987, IEEE Transactions on Electron Devices.
[12] B. Iniguez,et al. Finite Element Simulations of Parasitic Capacitances Related to Multiple-Gate Field-Effect Transistors Architectures , 2008, 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.
[13] D. Flandre,et al. Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs , 2003, IEEE Electron Device Letters.
[14] V. Kilchytska,et al. Perspective of FinFETs for analog applications , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
[15] Steve S. Chung,et al. A new approach to determine the drain-and-source series resistance of LDD MOSFET's , 1993 .
[16] R. Rooyackers,et al. A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node , 2004, IEEE Electron Device Letters.
[17] E. Dubois,et al. Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate , 2004, IEEE Electron Device Letters.
[18] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs: device design guidelines , 2002 .
[19] K. F. Lee,et al. Impact of distributed gate resistance on the performance of MOS devices , 1994 .
[20] Denis Flandre,et al. FinFET analogue characterization from DC to 110 GHz , 2005 .
[21] J.-P. Raskin,et al. Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization , 2006, IEEE Transactions on Electron Devices.
[22] Jean-Pierre Raskin,et al. Dynamic threshold voltage MOS in partially depleted SOI technology: a wide frequency band analysis , 2005 .
[23] Mansun Chan,et al. Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs , 2007, IEEE Transactions on Electron Devices.
[24] Chenming Hu,et al. SOI thermal impedance extraction methodology and its significance for circuit simulation , 2001 .
[25] William Redman-White,et al. Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques , 1996 .
[26] C.R. Cleavelin,et al. Body effect in tri- and pi-gate SOI MOSFETs , 2004, IEEE Electron Device Letters.
[27] Byung-Gook Park,et al. Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile , 2002 .
[28] R. Howes,et al. A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's , 1992 .
[29] Jean-Pierre Colinge,et al. Silicon-on-insulator 'gate-all-around' MOS device , 1990, 1990 IEEE SOS/SOI Technology Conference. Proceedings.
[30] Sorin Cristoloveanu,et al. Silicon on insulator technologies and devices: from present to future , 2001 .
[31] M. Jurczak,et al. Silicon-on-Nothing (SON)-an innovative process for advanced CMOS , 2000 .
[32] W. Redman-White,et al. Identification of thermal and electrical time constants in SOIMOSFETS from small signal measurements , 1993, ESSDERC '93: 23rd European solid State Device Research Conference.
[33] Tsu-Jae King,et al. A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain , 2005, IEEE Transactions on Electron Devices.
[34] Jean-Pierre Raskin,et al. High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors , 2008 .
[35] Jean-Pierre Raskin,et al. New RF extrinsic resistances extraction procedure for deep-submicron MOS transistors , 2010 .
[36] G. Pailloncy,et al. High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices , 2008, IEEE Electron Device Letters.
[37] Denis Flandre,et al. Silicon-on-Nothing MOSFETs: An efficient solution for parasitic substrate coupling suppression in SOI devices , 2008 .
[38] G. Ghibaudo,et al. Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs , 2004, IEEE Electron Device Letters.
[39] A. Mercha,et al. "Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS , 2003 .
[40] Juin J. Liou,et al. Simple method for extracting the difference between the drain and source series resistances in MOSFETs , 1994 .
[41] J. Larson,et al. Overview and status of metal S/D Schottky-barrier MOSFET technology , 2006, IEEE Transactions on Electron Devices.
[42] C. Faulkner,et al. Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS , 2003 .
[43] F.H. De La Moneda,et al. Measurement of MOSFET constants , 1982, IEEE Electron Device Letters.
[44] D. Flandre,et al. Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs , 2002, 32nd European Solid-State Device Research Conference.
[45] R. F. Motta,et al. A new method to determine MOSFET channel length , 1980, IEEE Electron Device Letters.
[46] E. Nowak,et al. High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[47] N. Collaert,et al. Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.
[48] J.-P. Raskin,et al. Revised RF Extraction Methods for Deep Submicron MOSFETs , 2008, 2008 European Microwave Integrated Circuit Conference.
[49] A. Fox,et al. High-frequency performance of dopant-segregated NiSi S/D SOI SB-MOSFETs , 2009, 2009 Proceedings of the European Solid State Device Research Conference.
[50] M. Fritze,et al. High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz , 2004, IEEE Electron Device Letters.
[51] D. Flandre,et al. AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs , 2004, IEEE Electron Device Letters.
[52] V. Kilchytska,et al. Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk , 2007, IEEE Electron Device Letters.
[53] Sorin Cristoloveanu,et al. Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .
[54] J. Raskin,et al. Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling , 1998 .
[55] J.-P. Raskin,et al. High-Frequency Noise Performance of 60-nm Gate-Length FinFETs , 2008, IEEE Transactions on Electron Devices.
[56] Cor Claeys,et al. Gate induced floating body effects in TiN/SiON and TiN/HfO2 gate stack triple gate SOI nFinFETs , 2007 .
[57] Hiroshi Iwai,et al. On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors , 2006 .
[58] R.L. Johnston,et al. Experimental derivation of the source and drain resistance of MOS transistors , 1980, IEEE Transactions on Electron Devices.
[59] F. Danneville,et al. Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface , 2009, IEEE Electron Device Letters.
[60] D. Flandre,et al. Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects , 2005, IEEE Electron Device Letters.
[61] F. Danneville,et al. RF Small-Signal Analysis of Schottky-Barrier p-MOSFET , 2008, IEEE Transactions on Electron Devices.
[62] N. Fel,et al. A New Approach for SOI Devices Small-Signal Parameters Extraction , 2000 .
[63] Gerard Ghibaudo,et al. Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides , 2003 .
[64] Denis Flandre,et al. Substrate-related output conductance frequency response of FD SOI MOSFETs: influence of channel length and substrate temperature , 2007 .
[65] F. Danneville,et al. Low Temperature Implementation of Dopant-Segregated Band-edge Metallic S/D junctions in Thin-Body SOI p-MOSFETs , 2007, 2007 IEEE International Electron Devices Meeting.
[66] G.A. Brown,et al. Correcting effective mobility measurements for the presence of significant gate leakage current , 2003, IEEE Electron Device Letters.
[67] G. Pailloncy,et al. Static and High-Frequency Behavior and Performance of Schottky-Barrier p-MOSFET Devices , 2007, IEEE Transactions on Electron Devices.