Design automation towards reliable analog integrated circuits
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[1] Georges Gielen,et al. Methodology for fast identification of EMIinduced operating point shift in analogue circuits , 2007 .
[2] Chenming Hu,et al. Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.
[3] Montserrat Nafría,et al. Worn-out oxide MOSFET characteristics: Role of gate current and device parameters on a current mirror , 2007, Microelectron. Reliab..
[4] Chenming Hu,et al. Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.
[5] J. Stathis. Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits , 2001 .
[6] A. S. Poulton. Effect of conducted EMI on the DC performance of operational amplifiers , 1994 .
[7] Yu Cao,et al. Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.
[8] Jordi Suñé,et al. Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability , 2005, Microelectron. Reliab..
[9] N. Mielke,et al. Universal recovery behavior of negative bias temperature instability [PMOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.
[10] I. Kurachi,et al. Physical model of drain conductance, g/sub d/, degradation of NMOSFET's due to interface state generation by hot carrier injection , 1994 .
[11] Georges G. E. Gielen,et al. Stochastic circuit reliability analysis , 2011, 2011 Design, Automation & Test in Europe.
[12] Georges G. E. Gielen,et al. Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies , 2008, 2008 Design, Automation and Test in Europe.
[13] D. Schroder,et al. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .
[14] Boris Murmann. Digitally Assisted Analog Circuits , 2006, IEEE Micro.
[15] James H. Stathis,et al. The negative bias temperature instability in MOS devices: A review , 2006, Microelectron. Reliab..
[16] Yu Cao,et al. An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[17] Georges G. E. Gielen,et al. Efficient reliability simulation of analog ICs including variability and time-varying stress , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[18] Guido Groeseneken,et al. Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study , 2002, Microelectron. Reliab..
[19] Georges Gielen,et al. NBTI model for analogue IC reliability simulation , 2010 .
[20] J. Stathis. Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).
[21] D. Kwong,et al. Dynamic NBTI of PMOS transistors and its impact on device lifetime , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[22] Georges G. E. Gielen,et al. Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.