Design driven partitioning

A new approach for partitioning VLSI digital integrated circuits is presented. In contrast to known approaches, which use only topological information, the presented method also exploits specific information about design modules and higher-level design structure. Based on this knowledge, the design-driven procedure creates a cluster structure that incorporates the inherent design relationships (e.g. signal flow, logic blocks) in the best way possible. Followed by standard iterative improvement algorithms, partitions are produced that outperform many partitioning approaches published before. Because of its linear time complexity, the presented clustering strategy is able to handle very large designs. Due to its modular structure, it can be easily extended to incorporate special design features or target architectures such as emulation systems.

[1]  Andrew B. Kahng,et al.  Fast spectral methods for ratio cut partitioning and clustering , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[2]  Jason Cong,et al.  Net partitions yield better module partitions , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[3]  Abbas El Gamal,et al.  Min-cut replication in partitioned networks , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Ernst G. Ulrich,et al.  Clustering and linear placement , 1972, DAC '72.

[5]  Martine D. F. Schlag,et al.  Spectral K-Way Ratio-Cut Partitioning and Clustering , 1993, 30th ACM/IEEE Design Automation Conference.

[6]  Hans Jürgen Prömel,et al.  Finding clusters in VLSI circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[7]  D. F. Wong,et al.  Efficient network flow based min-cut balanced partitioning , 1994, ICCAD 1994.

[8]  David A. Plaisted,et al.  A Heuristic Algorithm for Small Separators in Arbitrary Graphs , 1990, SIAM J. Comput..

[9]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[10]  Baruch Awerbuch,et al.  Sparse partitions , 1990, Proceedings [1990] 31st Annual Symposium on Foundations of Computer Science.

[11]  Mary Jane Irwin,et al.  A new optimization driven clustering algorithm for large circuits , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[12]  D. R. Fulkerson,et al.  Flows in Networks. , 1964 .

[13]  Chung-Kuan Cheng,et al.  Ratio cut partitioning for hierarchical designs , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Frank Thomson Leighton,et al.  Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms , 1989, 26th ACM/IEEE Design Automation Conference.

[15]  Baldomir Zajc,et al.  Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect , 1994, 31st Design Automation Conference.

[16]  Brian L. Mark,et al.  An efficient eigenvector approach for finding netlist partitions , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Chung-Kuan Cheng,et al.  Circuit Partitioning for Huge Logic Emulation Systems , 1994, 31st Design Automation Conference.

[18]  Andrew B. Kahng,et al.  A General Framework For Vertex Orderings, With Applications To Netlist Clustering , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[19]  Shoab Ahmed Khan,et al.  System Partitioning of MCMs for Low Power , 1995, IEEE Des. Test Comput..

[20]  Robert K. Brayton,et al.  On clustering for minimum delay/ara , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[21]  A. Richard Newton,et al.  A cell-replicating approach to minicut-based circuit partitioning , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[22]  Youssef Saab Post-analysis-based clustering dramatically improves the Fiduccia-Mattheyses algorithm , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[23]  Jason Cong,et al.  Acyclic Multi-Way Partitioning of Boolean Networks , 1994, 31st Design Automation Conference.

[24]  Ernest S. Kuh,et al.  Quadratic Boolean Programming for Performance-Driven System Partitioning , 1993, 30th ACM/IEEE Design Automation Conference.

[25]  Chung-Kuan Cheng,et al.  A two-level two-way partitioning algorithm , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[26]  Gabriele Saucier,et al.  FPGA partitioning for critical paths , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[27]  Jason Cong,et al.  A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design , 1993, 30th ACM/IEEE Design Automation Conference.

[28]  Carl Sechen,et al.  Efficient and effective placement for very large circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Jason Cong,et al.  Random walks for circuit clustering , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[30]  Andrew B. Kahng,et al.  New spectral methods for ratio cut partitioning and clustering , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Laura A. Sanchis,et al.  Multiple-Way Network Partitioning , 1989, IEEE Trans. Computers.

[32]  S.,et al.  An Efficient Heuristic Procedure for Partitioning Graphs , 2022 .

[33]  Konrad Doll,et al.  Partitioning Very Large Circuits Using Analytical Placement Techniques , 1994, 31st Design Automation Conference.