Power andPerformance Analysis for Early Design Space Exploration

Early design space exploration is crucial to achieving optimal designs, when it is increasingly difficult to fit a design into a tight design space. System level exploration needs to be coupled with physical design considerations to guarantee design closure and time-to-market. This paper presents a methodology for early design space exploration aimed at power-delay trade-offs. The proposed methodology allows quick what-if analysis incorporating many design techniques. What-if analysis is performed on three ISCAS85 benchmark circuits to ascertain recipes for power or performance centric designs. Using the proposed methodology we demonstrate 32%, 17% and 32% reduction in power for 9%, 4.3% and 1.3% performance penalty respectively, the what-if analysis also shows 11.25%, 10.31% and 15.3% improvement in performance for 2.35%, 2.43% and 3.85% increase in power, respectively if the same circuits were made performance centric.

[1]  S. Hsu,et al.  A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS , 2005, IEEE Journal of Solid-State Circuits.

[2]  Poras T. Balsara,et al.  Power switch network design for MTCMOS , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[3]  Shishpal Rawat,et al.  EDA challenges facing future microprocessor design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Michael Gschwind,et al.  New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors , 2003, IBM J. Res. Dev..

[5]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[6]  Kurt Keutzer,et al.  System-Level Performance Modeling with BACPAC - Berkeley Advanced Chip Performance Calculator , 1999 .

[7]  Narayanan Vijaykrishnan,et al.  Impact of technology scaling in the clock system power , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[8]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[9]  S. Rusu,et al.  Trends and challenges in VLSI technology scaling towards 100 nm , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[10]  Stefan Rusu.  Trends and challenges in VLSI technology scaling towards 100nm , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[11]  S. Borkar,et al.  Dynamic-sleep transistor and body bias for active leakage power control of microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[12]  Justin E. Harlow.  Toward design technology in 2020: trends, issues, and challenges [VLSI design] , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[13]  Yu (Kevin) Cao,et al.  What is Predictive Technology Model (PTM)? , 2009, SIGD.

[14]  David Howard,et al.  Challenges in sleep transistor design and implementation in low-power designs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[15]  Bram Nauta,et al.  Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract) , 2002, ASP-DAC/VLSI Design.

[16]  Gregory A. Northrop,et al.  A semi-custom design flow in high-performance microprocessor design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[17]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[18]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[19]  T. Chen,et al.  Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.