Testing Nanoarrays Fault Tolerance

The interesting expectations on nanoarray based circuits are counterbalanced by critical issues related to reliability. Nanowires and active devices currently cannot rely on a mature technology and high rates of defects are still to be expected. Our approach to evaluate the effects on nanoarray based circuits behavior consists in simulating at switch level the precise behavior of the circuit considering a statistical distribution of faults throughout the tile area. We are able to reckon the output error rate of nanoarray circuits as a function of defective rates and defect distribution giving to both technologists and architects directions to find possible solutions