A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS

CMOS circuits operating up to 60GHz have been demonstrated to satisfy the market demand for high data rates and frequency bandwidths [1–6]. However, 60GHz products need an improvement in power performance as well as transistor reliability for large signal operation. Moreover, Class-A or Class-AB power amplifiers (PA) are mandatory to overcome the difficulty of the limited maximum available gain (MAG) at mm-Wave frequencies [1–6] and the high linearity required by the OFDM modulation used in the IEEE 802.15.3c wireless HD standard. That means a maximum drain-source voltage swing of twice the DC voltage, which introduces specific design or supply voltage in order to respect reliability constraints [1,7]. This paper describes a PA with 8 power-combined ways and cascode topology in a 7-metal-layer 65nm CMOS process which covers the full band for 60GHz wireless applications. The presented circuit operates at a standard supply of 1.2V or 1.8V, and achieves a saturated output power of 16.6dBm and 18.1dBm respectively. The measured output power is high for CMOS while insuring reliability for time-dependent dielectric breakdown (TDDB) and hot-carrier-injection (HCI) degradation.

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