Efficient hardware solution for low power and adaptive image-compression in WSN

In this paper, we present and evaluate a hardware implementation for user-driven and packet-loss tolerant image compression, especially designed to enable low-power image compression and communication over wireless sensors networks (WSNs). The proposed compression scheme, presented as a CMOS circuit, is intended to be embedded in the camera sensor. It will be considered as a co-processor for tasks related with image compression and data packetization, which unloads the main microcontroller so that it will spend less time in active mode. The interest of our solution is twofold. First, compression settings can be changed at runtime (upon reception of a request message sent by an end-user or according to the internal state of the camera sensor node). Second, the image compression chain includes a (block of) pixel interleaving scheme which significantly improves the robustness against packet loss in image communication. The main part of this paper focuses on the specification and the performances analysis of this solution when implemented on FPGA and ASIC circuits.

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