HySIM: Towards a Scalable, Accurate and Fast Simulator for Manycore Processors

Simulation is the primary means to explore the design space of computer architecture. As the number of cores on a die increases, and the use of heterogeneous cores and on-chip networks leads to more and more complex systems, fast and cycle accurate simulation presents a formidable challenge. In this paper we propose the rationale for and design of a hybrid simulator called HySIM that takes RAMP Gold and moves the timing model of the memory subsystem to the host. This has four important advantages rst, it makes it possible to use multiple FPGAs in order to scale to a large number of cores, including heterogeneous cores and processors with hardware accelerators; second, it enables the modeling of detailed cache-coherence protocols by interfacing the simulator to a memory model such as Ruby; third, it provides a cycle-accurate model for the on-chip network that is exible enough to support dierent topologies, routing schemes, and router micro-architectures; and fourth, it frees up resources on the FPGA to increase the number of physical cores or to incorporate an on-chip L1 cache. We present preliminary results to validate HySIM and describe ongoing eort to improve its performance.