Performance evalulation of different routing algorithms in Network on Chip

Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on Chip (SoC). By the developments achieved in integrated circuits (IC) manufacturing there have been attempts to design vast amounts of network on the chips in order to achieve more efficient and optimized chips. A better routing algorithm can enhance the performance of NoC. XY routing algorithm is a distributed deterministic algorithm. Odd-Even (OE) routing algorithm is distributed adaptive routing algorithm with deadlock-free ability. Every NoC should satisfy some performance requirements like low latency, high throughput and low network power. Here we demonstrated the impact of traffic load variations on average latency, average throughput and total network power for two routing algorithms XY and OE on a 3×3 2-dimensional mesh topology. The simulations have been performed on NIRGAM NoC simulator version 2.1 for constant bit rate (CBR) traffic condition. The simulation results contains overall average latency (clock cycles per packet), average throughput (in Gbps) and total network power (in mW). Performance metrics (P) is calculated for both routing algorithms and compared.

[1]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[2]  José Duato,et al.  An Efficient Implementation of Distributed Routing Algorithms for NoCs , 2008 .

[3]  Ming Li,et al.  DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[4]  Ayas Kanta Swain,et al.  Performance assessment of different Network-on-Chip topologies , 2014, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS).

[5]  Hamid Sarbazi-Azad,et al.  Performance comparison of partially adaptive routing algorithms , 2006, 20th International Conference on Advanced Information Networking and Applications - Volume 1 (AINA'06).

[6]  José Duato,et al.  Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs , 2009 .

[7]  Zhonghai Lu,et al.  Using wormhole switching for networks on chip : feasibility analysis and microarchitecture adaptation , 2005 .

[8]  Mahendra A. Gaikwad,et al.  Comparative study of switching techniques for network-on-chip architecture , 2011, ICCCS '11.

[9]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[10]  Natalie D. Enright Jerger,et al.  On-Chip Networks , 2009, On-Chip Networks.

[11]  José Duato,et al.  An Efficient Implementation of Distributed Routing Algorithms for NoCs , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[12]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[13]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[14]  A. Arul,et al.  Analysis & Design of Network in Reusable Sub-Systems , 2009 .

[15]  Vincenzo Catania,et al.  Application Specific Routing Algorithms for Networks on Chip , 2009, IEEE Transactions on Parallel and Distributed Systems.

[16]  Axel Jantsch,et al.  Networks on chip , 2003 .

[17]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[18]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[19]  Antonio Robles,et al.  A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms , 2012, IEEE Transactions on Parallel and Distributed Systems.

[20]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[21]  Ligang Hou,et al.  Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3X3 Mesh Topology Network-on-Chip , 2009, 2009 WRI Global Congress on Intelligent Systems.

[22]  Masaru Fukushi,et al.  Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels , 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[23]  Juha Plosila,et al.  Network on Chip Routing Algorithms , 2006 .

[24]  M. A. Gaikwad,et al.  Review of XY Routing Algorithm for Network-on-Chip Architecture , 2012 .

[25]  SDMCET Dharwad.  Design and Implementation of Minimal adaptive West first algorithm for NoC Router Architecture , 2013 .

[26]  Wayne Luk,et al.  Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network , 2011, IEEE Transactions on Industrial Electronics.

[27]  Jie Wu,et al.  A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model , 2003, IEEE Trans. Computers.

[28]  Vincenzo Catania,et al.  Bandwidth-aware routing algorithms for networks-on-chip platforms , 2009, IET Comput. Digit. Tech..

[29]  Vincenzo Catania,et al.  Neighbors-on-Path: A New Selection Strategy for On-Chip Networks , 2006, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia.

[30]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[31]  Axel Jantsch,et al.  Network on Chip , 2002 .

[32]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1992, ISCA '92.

[33]  Avinoam Kolodny,et al.  Centralized Adaptive Routing for NoCs , 2010, IEEE Computer Architecture Letters.

[34]  Gerard J. M. Smit,et al.  A virtual channel router for on-chip networks , 2004, IEEE International SOC Conference, 2004. Proceedings..

[35]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[36]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.