A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fast- settling routing in high speed SAR ADCs
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Jun Xu | Ning Li | Fan Ye | Junyan Ren | Huabin Chen | Jixuan Xiang | Chixiao Chen
[1] Chung-Ming Huang,et al. A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[2] Rui Paulo Martins,et al. A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure , 2012, 2012 Symposium on VLSI Circuits (VLSIC).
[3] Yusuf Leblebici,et al. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS , 2013, IEEE Journal of Solid-State Circuits.
[4] Rui Paulo Martins,et al. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.
[5] Shunli Ma,et al. A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).