A Fault tolerant architecture of nine-level inverter with single and multiple switch fault-tolerance capabilities

Architectural development in the domain of multilevel inverters has seen tremendous interest from both academia and industry. On account of the low reliability of the semiconductor switches, multilevel inverters have been designed keeping in mind two essential characteristics which are: Reduced device count and fault tolerance characteristics. In regards to this, a novel multilevel inverter topology has been proposed in this paper. The topology is able to operate under both symmetrical and asymmetrical mode of operation. Also, the architecture of the developed topology allows for inherent reduced capacitor voltage ripple. Further, redundant leg architecture is added to the already proposed topology to incorporate fault tolerance characteristics. Single and multiple switches failure are considered on the proposed fault tolerant topology. The robustness of the proposed topology is verified by the obtained simulation results. In the end, quantitative and qualitative comparison of the proposed topology proves its superiority over the recently presented topologies.