Simulations of Damage, Crack Initiation, and Propagation in Interlayer Dielectric Structures: Understanding Assembly-Induced Fracture in Dies

Performance enhancement by lowering the dielectric constant of interlayer dielectric (ILD) materials often compromises the mechanical integrity of the dielectric stack. At the present time, fracture in the ILD stacks induced by assembly to either an organic substrate or a die stack (3-D) is an important reliability consideration. These interactions include what is popularly referred to as the chip-package interactions. In this paper, we develop insights on the potential crack initiation site within the ILD, die-substrate geometrical parameters that cause most damage, as well as insights on the manufacturing process that is critical to failure. Towards this end, we utilize analytical models based on classical elasticity theory as well as sophisticated numerical techniques that are capable of nucleating and propagating cracks at arbitrary locations within the structure without remeshing. Specifically, we analytically estimate the strength of singularities at all the possible multimaterial corners in the ILD stack to provide insight on the likely damage nucleation sites for various material configurations in the ILD stack. Two novel numerical approaches are used for fracture simulation. In the first, cracks are modeled as discontinuous enrichments over an underlying continuous behavioral approximation. In the second approach, the underlying material description is enriched with a cohesive damage description whose stiffness is evolved according to a prescribed damage law. Multilevel finite-element models are used to determine the load imposed on the ILD structure by the substrate. Maximum damage induced in the ILD stack by the above load is used as an indicator of the reliability risk. Parametric simulations are conducted by varying ILD material, die size, die thickness, as well as the solder material. Through analytical models of bonded assemblies, we identify groups of relevant dimensionless parameters to relate the numerically estimated damage in ILD stacks to the die/substrate material and geometrical parameters. We demonstrate that the damage in the ILD stack is least when the flexural rigidity of the die is matched to that of the assembled substrate. We also demonstrate that ILD damage is only weakly correlated to shear deformation on the die surface due to assembly. We generalize the above observations into mathematical fits (for use as design rules) relating damage in ILD stacks to ILD material choice, relative substrate flexural rigidity, and die size.

[1]  F. Erdogan,et al.  Stress singularities in a two-material wedge , 1971 .

[2]  Abhishek Tambat Explicit geometry based enriched field approximations , 2013 .

[3]  Mark A Fleming,et al.  Meshless methods: An overview and recent developments , 1996 .

[4]  K. Banerji,et al.  Constitutive relations for tin-based-solder joints , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.

[5]  Les A. Piegl,et al.  The NURBS Book , 1995, Monographs in Visual Communication.

[6]  I. Babuska,et al.  The partition of unity finite element method: Basic theory and applications , 1996 .

[7]  G. Subbarayan,et al.  CAD inspired hierarchical partition of unity constructions for NURBS‐based, meshless design, analysis and optimization , 2007 .

[8]  Paul S. Ho,et al.  Chip‐Packaging Interaction and Reliability Impact on Cu/Low k Interconnects , 2006 .

[9]  Andrzej Seweryn,et al.  Elastic stress singularities and corresponding generalized stress intensity factors for angular corners under various boundary conditions , 1996 .

[10]  Ganesh Subbarayan,et al.  NURBS-based solutions to inverse boundary problems in droplet shape prediction , 2000 .

[11]  T. Hughes,et al.  Isogeometric analysis : CAD, finite elements, NURBS, exact geometry and mesh refinement , 2005 .

[12]  Ganesh Subbarayan,et al.  A study of multiple singularities in multi-material wedges and their use in analysis of microelectronic interconnect structures , 2007 .

[13]  Ted Belytschko,et al.  Numerical integration of the Galerkin weak form in meshfree methods , 1999 .

[14]  V. Gupta,et al.  Constitutive and Aging Behavior of Sn3.0Ag0.5Cu Solder Alloy , 2009, IEEE Transactions on Electronics Packaging Manufacturing.

[15]  Karen Maex,et al.  Short-ranged structural rearrangement and enhancement of mechanical properties of organosilicate glasses induced by ultraviolet radiation , 2006 .

[16]  Sean W. King,et al.  Rigidity Percolation in Plasma Enhanced Chemical Vapor Deposited a-SiC:H Thin Films , 2010 .

[17]  Ganesh Subbarayan,et al.  Hierarchical Partition of Unity Field Compositions (HPFC) for Optimal Design in the Presence of Cracks , 2010 .

[18]  Paul S. Ho,et al.  Packaging effects on reliability of Cu/low-k interconnects , 2003 .

[19]  K. Kohmura,et al.  Novel self-assembled ultra-low-k porous silica films with high mechanical strength for 45 nm BEOL technology , 2003, IEEE International Electron Devices Meeting 2003.

[20]  Guotao Wang,et al.  Chip-packaging interaction: a critical concern for Cu/low k packaging , 2005, Microelectron. Reliab..

[21]  David L. Chopp,et al.  Modeling thermal fatigue cracking in integrated circuits by level sets and the extended finite element method , 2003 .

[22]  D. Munz,et al.  Stresses near the edge of bonded dissimilar materials described by two stress intensity factors , 1993 .

[23]  José M. Martínez-Esnaola,et al.  Fracture characterization in patterned thin films by cross-sectional nanoindentation , 2006 .

[24]  Ganesh Subbarayan,et al.  Hierarchical field compositions for discontinuous enrichment and system-level synthesis , 2008 .

[25]  James R. Rice,et al.  Elastic Fracture Mechanics Concepts for Interfacial Cracks , 1988 .

[26]  Xuefeng Zhang,et al.  Chip Package Interaction and mechanical reliability impact on Cu/ultra low-k interconnects in Flip Chip package , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[27]  C. W. Nelson,et al.  Thermal stress in bonded joints , 1979 .

[28]  Z. Suo,et al.  Split singularities: stress field near the edge of a silicon die on a polymer substrate , 1998 .

[29]  Michael Lane,et al.  Adhesion and debonding of multi-layer thin film structures , 1998 .

[30]  Arvind Kumar,et al.  Three-dimensional integrated circuits , 2006, IBM J. Res. Dev..

[31]  Ganesh Subbarayan,et al.  Constructive solid analysis: a hierarchical, geometry-based meshless analysis procedure for integrated design and analysis , 2004, Comput. Aided Des..