Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic

Adiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is presented, and to validate its performance, a 5/spl times/5 ternary digit multiplier is designed and implemented in a 0.7-/spl mu/m CMOS technology. Results show a satisfactory power saving with respect to conventional and other quasi-adiabatic binary multipliers, and a decrease of the area needed with respect to a fully adiabatic binary one.