Comparative Evaluation of Kelvin Connection for Current Sharing of Multi-Chip Power Modules

High-capacity power module with multiple parallel chips is a key component for renewable energy applications. Imbalance electro-thermal stresses among the parallel chips challenge the high-capacity power modules. Advanced packaging is considered as a promising solution toward higher capacity of power modules. In this paper, based on a commercial wire-bonding packaging, to enhance the current sharing in the multi-chip insulated-gate bipolar transistor (IGBT) power module, the capability of Kelvin connection to overcome the imbalance transient current and switching loss among parallel chips is comparatively surveyed. Taking parasitics into account, equivalent electric circuit and finite element analysis are proposed to illustrate the influences of Kelvin connection. Based on the customized power modules and a double-pulse test rig, simulation and experimental results are presented to comprehensively demonstrate the current sharing of parallel chips affected by Kelvin connection. It reveals the Kelvin connection can boost switching speed and reduce switching loss. However, the capability to eliminate imbalance current by using Kelvin connection is limited. Optimized direct bonded copper (DBC) layout to eliminate the asymmetric parallel loops is needed for multi-chip modules.

[1]  Khai D. T. Ngo,et al.  Passive Balancing of Peak Currents Between Paralleled MOSFETs With Unequal Threshold Voltages , 2017, IEEE Transactions on Power Electronics.

[2]  Li Ran,et al.  The Effect of Electrothermal Nonuniformities on Parallel Connected SiC Power Devices Under Unclamped and Clamped Inductive Switching , 2016, IEEE Transactions on Power Electronics.

[3]  Hui Li,et al.  Changes and challenges of photovoltaic inverter with silicon carbide device , 2017 .

[4]  Li Ran,et al.  Design and evaluation of SiC multichip power module with low and symmetrical inductance , 2019, The Journal of Engineering.

[5]  Stig Munk-Nielsen,et al.  Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs , 2017, 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe).

[6]  Xiongfei Wang,et al.  Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs , 2016, IEEE Transactions on Power Electronics.

[7]  Longya Xu,et al.  A Double-End Sourced Wire-Bonded Multichip SiC MOSFET Power Module With Improved Dynamic Current Sharing , 2017, IEEE Journal of Emerging and Selected Topics in Power Electronics.

[8]  Huai Wang,et al.  Comprehensive investigation on current imbalance among parallel chips inside MW-scale IGBT power modules , 2015, 2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia).

[9]  Stefanos Manias,et al.  Forced Current Balancing of Parallel-Connected SiC JFETs During Forward and Reverse Conduction Mode , 2017, IEEE Transactions on Power Electronics.

[10]  Khai D. T. Ngo,et al.  Balancing of Peak Currents Between Paralleled SiC MOSFETs by Drive-Source Resistors and Coupled Power-Source Inductors , 2017, IEEE Transactions on Industrial Electronics.

[11]  Alex Q. Huang,et al.  Power Semiconductor Devices for Smart Grid and Renewable Energy Systems , 2017, Proceedings of the IEEE.

[12]  Dushan Boroyevich,et al.  Advances in Power Conversion and Drives for Shipboard Systems , 2015, Proceedings of the IEEE.

[13]  Xiangyu Liu,et al.  Concerning layout synthesis for power electronic multi-chip modules , 2010, 2010 IEEE 12th Workshop on Control and Modeling for Power Electronics (COMPEL).

[14]  Leon M. Tolbert,et al.  Stray Inductance Reduction of Commutation Loop in the P-cell and N-cell-Based IGBT Phase Leg Module , 2014, IEEE Transactions on Power Electronics.

[15]  Xiongfei Wang,et al.  Effects of Auxiliary-Source Connections in Multichip Power Module , 2017 .

[16]  Frede Blaabjerg,et al.  New layout concepts in MW-scale IGBT modules for higher robustness during normal and abnormal operations , 2016, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC).

[17]  Hans-Peter Nee,et al.  Analysis and Experimental Verification of the Influence of Fabrication Process Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-Connected SiC JFETs , 2014, IEEE Transactions on Power Electronics.

[18]  Leon M. Tolbert,et al.  A compact planar Rogowski coil current sensor for active current balancing of parallel-connected Silicon Carbide MOSFETs , 2014, 2014 IEEE Energy Conversion Congress and Exposition (ECCE).

[19]  Li Ran,et al.  Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS , 2016, IEEE Transactions on Industrial Electronics.

[20]  Yang Xue,et al.  Active compensation of current unbalance in paralleled silicon carbide MOSFETs , 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.

[21]  Hans-Peter Nee,et al.  Challenges Regarding Parallel Connection of SiC JFETs , 2013 .