The half-V/sub cc/ sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V/sub cc/ generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line. >
[1]
S. Shinozaki,et al.
A 50-μA standby 1M x 1/256K×4 CMOS DRAM with high-speed sense amplifier
,
1986
.
[2]
K. Rainer,et al.
A sense-signal doubling circuit for DRAMs
,
1987,
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[3]
H. H. Chao,et al.
Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs
,
1984
.
[4]
L. G. Heller,et al.
High sensitivity charge-transfer sense amplifier
,
1975
.
[5]
Koichiro Mashiko,et al.
A 90ns 4Mb DRAM in a 300 mil DIP
,
1987,
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.