A method of representative fault selection in digital circuits for ATPG

A new method of representative fault selection in digital circuits based on the concepts of test equivalent and test implied faults is introduced in order to minimise the number of target faults to be considered in ATPG and fault simulation. Experimental results on a set of ISCAS benchmark combinational and sequential circuits have shown a significant reduction in the number of target faults when compared with other recently published techniques.<<ETX>>

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